Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

29.2.4. SDRAM Clocks

You can configure the HPS component with up to six FPGA-to-HPS SDRAM clocks.

Each command channel to the SDRAM controller has an individual clock source from the FPGA fabric. The interface clock is always supplied by the FPGA fabric, with clock crossing occurring on the HPS side of the boundary.

The FPGA-to-HPS SDRAM clocks are driven by soft logic in the FPGA fabric.

  • f2h_sdram0_clock—SDRAM clock for port 0
  • f2h_sdram1_clock—SDRAM clock for port 1
  • f2h_sdram2_clock—SDRAM clock for port 2
  • f2h_sdram3_clock—SDRAM clock for port 3
  • f2h_sdram4_clock—SDRAM clock for port 4
  • f2h_sdram5_clock—SDRAM clock for port 5