Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

4.2.1.2. Warm Reset Assertion Sequence

The following list describes the assertion steps for warm reset shown in the Warm Reset Timing Diagram:

  1. Optionally, handshake with the embedded trace router (ETR) and wait for acknowledge.
  2. Optionally, handshake with the FPGA fabric and wait for acknowledge.
  3. Optionally, handshake with the SDRAM controller, scan manager, and FPGA manager, and wait for acknowledges.
  4. Assert module resets (except the MPU watchdog timer resets when the MPU watchdog timers are the only request sources).
  5. Wait for 8 cycles and send a safe mode request to the clock manager.
  6. Wait for the greater of the nRST pin count + 256 stretch count, or the warm reset counter, or the clock manager safe mode acknowledge, then deassert all handshakes except warm reset ETR handshake (which is deasserted by software).
  7. Proceed to the “Cold and Warm Reset Deassertion Sequence” section using the following link.
Note: The nRST is a bidirectional signal that is driven out when a warm reset is generated in the chip.