Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

4.2.1.3. Cold and Warm Reset Deassertion Sequence

The following list describes the deassertion steps for both cold and warm reset shown in the Cold Reset Timing Diagram and Warm Reset Timing Diagram:

  1. Deassert L3 reset.
  2. Wait for 100 cycles. Deassert resets for miscellaneous-type and debug (cold only) modules.
  3. Wait for 200 cycles. Assert mpu_clkoff for CPU0 and CPU1.
  4. Wait for 32 cycles. Deassert resets for MPU modules.
  5. Wait for 32 cycles. Deassert mpu_clkoff for CPU0 and CPU1.
  6. Peripherals remain held in reset until software brings them out of reset.