Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

16.5.2. Indirect Read Operation with DMA Disabled

The following steps describe the general software flow to set up the quad SPI controller for indirect read operation with the DMA disabled:

  1. Perform the steps described in the Setting Up the Quad SPI Flash Controller section.
  2. Set the flash memory start address in the indrdstaddr register.
  3. Set the number of bytes to be transferred in the indrdcnt register.
  4. Set the indirect transfer trigger address in the indaddrtrig register.
  5. Set up the required interrupts through the irqmask register.
  6. If the watermark level is used, set the SRAM watermark level through the indrdwater register.
  7. Start the indirect read operation by setting the start field of the indrd register to 1.
  8. Either use the watermark level interrupt or poll the SRAM fill level in the sramfill register to determine when there is sufficient data in the SRAM.
  9. Issue a read transaction to the indirect address to access the SRAM. Repeat 8 if more read transactions are needed to complete the indirect read transfer.
  10. Either use the indirect complete interrupt to determine when the indirect read operation has completed or poll the completion status of the indirect read operation through the indirect completion status bit (ind_ops_done_status) of the indrd register.