Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

20.4.9. Clocks and Resets

The SPI controller uses the clock and reset signals shown in the following table.

Table 203.  SPI Controller Clocks and Resets
 

Master

Slave

SPI clock

spi_m_clk l4_main_clk

SPI bit-rate clock

sclk_out sclk_in

Reset

spim_rst_n spis_rst_n