Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

A.4.3.1. Boot Source I/O Mapping

The table below shows how the boot source signals are mapped to the I/O pins when the BSEL pins are configured.
Table 264.   Boot Source I/O Mappings
Note: "-" means that the pin is not used for that boot select interface.

Pin

Boot Interface Signals
NAND (BSEL[2:0] = 0x2 or 0x3) SD/MMC (BSEL[2:0] = 0x4 or 0x5) QSPI (BSEL[2:0] = 0x6 or 0x7)
MIXED1IO0 NAND_ALE - -
MIXED1IO1 NAND_CE - -
MIXED1IO2 NAND_CLE - -
MIXED1IO3 NAND_RE - -
MIXED1IO4 NAND_RB - -
MIXED1IO5 NAND_DQ0 - -
MIXED1IO6 NAND_DQ1 - -
MIXED1IO7 NAND_DQ2 - -
MIXED1IO8 NAND_DQ3 - -
MIXED1IO9 NAND_DQ4 - -
MIXED1IO10 NAND_DQ5 - -
MIXED1IO11 NAND_DQ6 - -
MIXED1IO12 NAND_DQ7 - -
MIXED1IO13 NAND_WP - -
MIXED1IO14 NAND_WE - -
MIXED1IO15 - - QSPI_IO0
MIXED1IO16 - - QSPI_IO1
MIXED1IO17 - - QSPI_IO2
MIXED1IO18 - - QSPI_IO3
MIXED1IO19 - - QSPI_SS0
MIXED1IO20 - - QSPI_CLK
MIXED1IO21 - - QSPI_SS1
FLASHIO0 - SDMMC_CMD -
FLASHIO1 - - -
FLASHIO2 - SDMMC_D0 -
FLASHIO3 - - -
FLASHIO4 - - -
FLASHIO5 - - -
FLASHIO6 - - -
FLASHIO7 - - -
FLASHIO8 - - -
FLASHIO9 - SDMMC_CLK -
FLASHIO10 - - -