Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 12/03/2024
Public

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Ixiasoft

Document Table of Contents

10.3.15.3.3. Configuring AxPROT[2:0] Sideband Signals for Coherent Accesses

The following list highlights how to correctly derive and apply the correct AxPROT settings for coherent accesses.
  • AxPROT[1] must be set to 0x0 for coherent accesses.
  • For FPGA masters, AxPROT[2:0] is applied in the FPGA fabric and can be set for each access.