Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

10.8. Clocks

Four synchronous clocks and two debug clocks are provided to the MPU subsystem.

Table 71.  MPU Subsystem Clocks

System Clock Name

Use

mpu_clk

Main clock for the MPU subsystem

mpu_periph_clk

Clock for peripherals inside the MPU subsystem

mpu_l2_ram_clk

Clock for the L2 cache and Accelerator Coherency Port (ACP) ID mapper

l4_mp_clk

Clock for the ACP ID mapper control slave

dbg_at_clk

Trace bus clock

dbg_clk

Debug clock