Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

17.2. DMA Controller Block Diagram and System Integration

The following figure shows a block diagram of the DMAC and how it integrates into the rest of the HPS system.

Figure 68. DMA Controller Connectivity

The l4_main_clk clock drives the DMA controller, controller logic, and all the interfaces. The DMA controller accesses the level 3 (L3) main switch with its 64‑bit AXI master interface.

The DMA controller provides the following slave interfaces:

  • Non‑secure slave interface
  • Secure slave interface

You can use these slave interfaces to access the registers that control the functionality of the DMA controller. Since the DMA controller supports some peripherals that do not comply with the Arm* DMA peripheral interface protocol, some adapters are developed to allow these peripherals to work with the DMAC.