Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

4.1.3. Module Reset Signals

The following tables list the module reset signals. The module reset signals are organized in groups for the MPU, peripherals, bridges.

In the following tables, columns marked for Cold Reset, Warm Reset, and Debug Reset denote reset signals asserted by each type of reset. For example, writing a 1 to the swwarmrstreq bit in the ctrl register resets all the modules that have a checkmark in the Warm Reset column.

The column marked for Software Deassert denotes reset signals that are left asserted by the reset manager.

Table 19.  MPU Group, Generated Module Resets

Module Reset Signal

Description

Reset Domain

Cold Reset

Warm Reset

Debug Reset

Software Deassert

mpu_cpu_rst_n[0] Resets each processor in the MPU System X X    
mpu_cpu_rst_n[1]

Resets each processor in the MPU

System

X X   X
mpu_wd_rst_n

Resets both per-processor watchdogs in the MPU

System

X X    
mpu_scu_periph_rst_n

Resets Snoop Control Unit (SCU) and peripherals

System

X X    
mpu_l2_rst_n

Level 2 (L2) cache reset

System

X X    
Table 20.  PER Group, Generated Module Resets

Module Reset Signal

Description

Reset Domain

Cold Reset

Warm Reset

Debug Reset

Software Deassert
emac_rst_n[1:0]

Resets each EMAC

System

X

X

  X
usb_rst_n[1:0]

Resets each USB

System

X

X

  X
nand_flash_rst_n

Resets NAND flash controller

System

X

X

  X
qspi_flash_rst_n

Resets quad SPI flash controller

System

X

X

  X
watchdog_rst_n[1:0]

Resets each system watchdog timer

System

X

X

  X
osc1_timer_rst_n[1:0]

Resets each OSC1 timer

System

X

X

  X
sp_timer_rst_n[1:0]

Resets each SP timer

System

X

X

  X
i2c_rst_n[3:0]

Resets each I2C controller

System

X

X

  X
uart_rst_n[1:0]

Resets each UART

System

X

X

  X
spim_rst_n[1:0]

Resets SPI master controller

System

X

X

  X
spis_rst_n[1:0]

Resets SPI slave controller

System

X

X

  X
sdmmc_rst_n

Resets SD/MMC controller

System

X

X

  X
can_rst_n[1:0]

Resets each CAN controller

System

X

X

  X
gpio_rst_n[2:0]

Resets each GPIO interface

System

X

X

  X
dma_rst_n

Resets DMA controller

System

X

X

  X
sdram_rst_n

Resets SDRAM subsystem (resets logic associated with cold or warm reset)

System

X

X

  X
Table 21.  PER2 Group, Generated Module Resets
Module Reset Signal Description Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
dma_periph_if_rst_n[7:0] DMA controller request interface from FPGA fabric to DMA controller System X X   X
Table 22.  Bridge Group, Generated Module Resets
Module Reset Signal Description Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
hps2fpga_bridge_rst_n Resets HPS-to-FPGA AMBA* Advanced eXtensible Interface ( AXI* ) bridge System X X   X
fpga2hps_bridge_rst_n Resets FPGA-to-HPS AXI* bridge System X X   X
lwhps2fpga_bridge_rst_n Resets lightweight HPS-to-FPGA AXI* bridge System X X   X
Table 23.  MISC Group, Generated Module Resets
Module Reset Signal Description Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
boot_rom_rst_n Resets boot ROM System X X    
onchip_ram_rst_n Resets on-chip RAM System X X    
sys_manager_rst_n Resets system manager (resets logic associated with cold or warm reset) System X X    
sys_manager_cold_rst_n Resets system manager (resets logic associated with cold reset only) System X      
fpga_manager_rst_n Resets FPGA manager System X X    
acp_id_mapper_rst_n Resets ACP ID mapper System X X    
h2f_rst_n Resets user logic in FPGA fabric (resets logic associated with cold or warm reset) System X X    
h2f_cold_rst_n Resets user logic in FPGA fabric (resets logic associated with cold reset only) System X      
rst_pin_rst_n Pulls nRST pin low System   X    
timestamp_cold_rst_n Resets debug timestamp to 0x0 System X      
clk_manager_cold_rst_n Resets clock manager (resets logic associated with cold reset only) System X      
scan_manager_rst_n Resets scan manager System X X    
frz_ctrl_cold_rst_n Resets freeze controller (resets logic associated with cold reset only) System X      
sys_dbg_rst_n Resets debug masters and slaves connected to L3 interconnect and level 4 (L4) buses System X X    
dbg_rst_n Resets debug components including DAP, trace, MPU debug logic, and any user debug logic in the FPGA fabric Debug X   X  
tap_cold_rst_n Resets portion of TAP controller in the DAP that must be reset on a cold reset TAP X      
sdram_cold_rst_n Resets SDRAM subsystem (resets logic associated with cold reset only) System X      
Table 24.  L3 Group, Generated Module Resets
Module Reset Signal Description Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
l3_rst_n Resets L3 interconnect and L4 buses System X X