Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

2.2.4.1. SDRAM Controller Subsystem

HPS and FPGA fabric masters have access to the SDRAM controller subsystem.

The SDRAM controller subsystem implements the following high‑level features:

  • Support for double data rate 2 (DDR2), DDR3, and low-power double data rate 2 (LPDDR2) devices
  • Error correction code (ECC) support, including calculation, single‑bit error correction and write-back, and error counters
  • Fully-programmable timing parameter support for all JEDEC‑specified timing parameters
  • All ports support memory protection and mutual accesses
  • FPGA fabric interface with up to six ports that can be combined for a data width up to 256-bits wide using Avalon-MM and AXI interfaces.

The SDRAM controller subsystem is composed of the SDRAM controller, DDR PHY, control and status registers and their associated interfaces.