Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

20.6. SPI Controller Address Map and Register Definitions

The address map and register definitions for the HPS-FPGA bridges consist of the following regions:

  • SPI Slave Module 0
  • SPI Slave Module 1
  • SPI Master Module 0
  • SPI Master Module 1