Cyclone® V Hard Processor System Technical Reference Manual
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Ixiasoft
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Ixiasoft
16.4.2.1.2. AHB*
FLASH erase operations, which may be required before a page write, are triggered by software using the documented programming interface. They are not issued automatically.
Once a page program cycle has been started, the QSPI Flash Controller will automatically poll for the write cycle to complete before allowing any further data slave interface accesses to complete. This is achieved by holding any subsequent AHB* direct accesses in wait state.