Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

16.4.5. Local Memory Buffer

The SRAM local memory buffer is a 128 by 32-bit (512 total bytes) memory and includes support for error correction code (ECC). The ECC logic provides outputs to notify the system manager when single-bit correctable errors are detected (and corrected) and when double-bit uncorrectable errors are detected. The ECC logic also allows the injection of single- and double-bit errors for test purposes.

You must initialize memory data before enabling ECC to prevent spurious ECC interrupts when you enable ECC for the first time.

Follow these steps to enable ECC:
  1. Turn on the ECC hardware, but disable the interrupts.
  2. Initialize the SRAM in the NAND.
  3. Clear the ECC event bits, because these bits may have become asserted after Step 1.
  4. Enable the ECC interrupts now that the ECC bits have been set.

The SRAM has two partitions, with the lower partition reserved for indirect read operations and the upper partition reserved for indirect write operations, as shown in the Quad SPI Flash Controller Block Diagram and System Integration section. The size of each partition is specified in the SRAM partition register (srampart), based on 32‑bit word sizes. The number of locations allocated to indirect read is (srampart +1); and the number of locations allocated to indirect write is (128 – srampart)54. For example, to specify four bytes of storage, write the value 1. The value written to the indirect read partition size field (addr) defines the number of entries reserved for indirect read operations. For example, write the value 32 (0x20) to partition the 128-entry SRAM to 32 entries (25%) for read usage and 96 entries (75%) for write usage.

54 You cannot allocate all of the SRAM for writes.