Cyclone® V Hard Processor System Technical Reference Manual

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ID 683126
Date 12/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone® V Hard Processor System Technical Reference Manual Revision History 2. Introduction to the Hard Processor System 3. Clock Manager 4. Reset Manager 5. FPGA Manager 6. System Manager 7. Scan Manager 8. System Interconnect 9. HPS-FPGA Bridges 10. Cortex®-A9 Microprocessor Unit Subsystem 11. CoreSight* Debug and Trace 12. SDRAM Controller Subsystem 13. On-Chip Memory 14. NAND Flash Controller 15. SD/MMC Controller 16. Quad SPI Flash Controller 17. DMA Controller 18. Ethernet Media Access Controller 19. USB 2.0 OTG Controller 20. SPI Controller 21. I2C Controller 22. UART Controller 23. General-Purpose I/O Interface 24. Timer 25. Watchdog Timer 26. CAN Controller 27. Introduction to the HPS Component 28. Instantiating the HPS Component 29. HPS Component Interfaces 30. Simulating the HPS Component 31. Register Address Map for Cyclone V HPS A. Booting and Configuration
2. Introduction to the Hard Processor System x
2.1. Features of the HPS 2.2. HPS Block Diagram and System Integration 2.3. Endian Support 2.4. Introduction to the Hard Processor System Address Map
2.2. HPS Block Diagram and System Integration x
2.2.1. HPS Block Diagram 2.2.2. Cortex-A9 MPCore 2.2.3. HPS Interfaces 2.2.4. System Interconnect 2.2.5. On-Chip Memory 2.2.6. Flash Memory Controllers 2.2.7. Support Peripherals 2.2.8. Interface Peripherals 2.2.9. CoreSight Debug and Trace
2.2.3. HPS Interfaces x
2.2.3.1. HPS–FPGA Memory-Mapped Interfaces 2.2.3.2. Other HPS Interfaces
2.2.4. System Interconnect x
2.2.4.1. SDRAM Controller Subsystem
2.2.4.1. SDRAM Controller Subsystem x
2.2.4.1.1. SDRAM Controller 2.2.4.1.2. DDR PHY
2.2.5. On-Chip Memory x
2.2.5.1. On-Chip RAM 2.2.5.2. Boot ROM
2.2.6. Flash Memory Controllers x
2.2.6.1. NAND Flash Controller 2.2.6.2. Quad SPI Flash Controller 2.2.6.3. SD/MMC Controller
2.2.7. Support Peripherals x
2.2.7.1. Clock Manager 2.2.7.2. Reset Manager 2.2.7.3. System Manager 2.2.7.4. Scan Manager 2.2.7.5. Timers 2.2.7.6. Watchdog Timers 2.2.7.7. DMA Controller 2.2.7.8. FPGA Manager
2.2.8. Interface Peripherals x
2.2.8.1. EMACs 2.2.8.2. USB Controllers 2.2.8.3. I2C Controllers 2.2.8.4. UARTs 2.2.8.5. CAN Controllers 2.2.8.6. SPI Master Controllers 2.2.8.7. SPI Slave Controllers 2.2.8.8. GPIO Interfaces
2.4. Introduction to the Hard Processor System Address Map x
2.4.1. HPS Address Spaces 2.4.2. HPS Peripheral Region Address Map
2.4.1. HPS Address Spaces x
2.4.1.1. SDRAM Address Space 2.4.1.2. MPU Address Space 2.4.1.3. L3 Address Space
3. Clock Manager x
3.1. Features of the Clock Manager 3.2. Clock Manager Block Diagram and System Integration 3.3. Functional Description of the Clock Manager 3.4. Clock Manager Address Map and Register Definitions
3.2. Clock Manager Block Diagram and System Integration x
3.2.1. L4 Peripheral Clocks
3.3. Functional Description of the Clock Manager x
3.3.1. Clock Manager Building Blocks 3.3.2. Hardware-Managed and Software-Managed Clocks 3.3.3. Clock Groups 3.3.4. Resets 3.3.5. Safe Mode 3.3.6. Interrupts 3.3.7. Clock Usage By Module
3.3.1. Clock Manager Building Blocks x
3.3.1.1. PLLs 3.3.1.2. FREF, FVCO, and FOUT Equations 3.3.1.3. Dividers 3.3.1.4. Clock Gating 3.3.1.5. Control and Status Registers
3.3.3. Clock Groups x
3.3.3.1. OSC1 Clock Group 3.3.3.2. Main Clock Group 3.3.3.3. Peripheral Clock Group
3.3.3.2. Main Clock Group x
3.3.3.2.1. Changing Values That Affect Main Clock Group PLL Lock
3.3.3.3. Peripheral Clock Group x
3.3.3.3.1. Flash Controller Clocks 3.3.3.3.2. SDRAM Clock Group
3.3.4. Resets x
3.3.4.1. Cold Reset 3.3.4.2. Warm Reset
4. Reset Manager x
4.1. Reset Manager Block Diagram and System Integration 4.2. Functional Description of the Reset Manager 4.3. Reset Manager Address Map and Register Definitions
4.1. Reset Manager Block Diagram and System Integration x
4.1.1. HPS External Reset Sources 4.1.2. Reset Controller 4.1.3. Module Reset Signals 4.1.4. Slave Interface and Status Register
4.1.3. Module Reset Signals x
4.1.3.1. Modules Requiring Software Deassert
4.2. Functional Description of the Reset Manager x
4.2.1. Reset Sequencing 4.2.2. Reset Pins 4.2.3. Reset Effects 4.2.4. Altering Warm Reset System Response 4.2.5. Reset Handshaking
4.2.1. Reset Sequencing x
4.2.1.1. Cold Reset Assertion Sequence 4.2.1.2. Warm Reset Assertion Sequence 4.2.1.3. Cold and Warm Reset Deassertion Sequence
5. FPGA Manager x
5.1. Features of the FPGA Manager 5.2. FPGA Manager Block Diagram and System Integration 5.3. Functional Description of the FPGA Manager 5.4. FPGA Manager Address Map and Register Definitions
5.3. Functional Description of the FPGA Manager x
5.3.1. FPGA Manager Building Blocks 5.3.2. FPGA Configuration 5.3.3. FPGA Status 5.3.4. Error Message Extraction 5.3.5. Boot Handshake 5.3.6. General Purpose I/O 5.3.7. Clock 5.3.8. Reset
5.3.1. FPGA Manager Building Blocks x
5.3.1.1. Fabric I/O 5.3.1.2. Monitor
5.3.2. FPGA Configuration x
5.3.2.1. Power Up Phase 5.3.2.2. Reset Phase 5.3.2.3. Configuration Phase 5.3.2.4. Initialization Phase 5.3.2.5. User Mode
6. System Manager x
6.1. Features of the System Manager 6.2. System Manager Block Diagram and System Integration 6.3. Functional Description of the System Manager 6.4. System Manager Address Map and Register Definitions
6.3. Functional Description of the System Manager x
6.3.1. Boot Configuration and System Information 6.3.2. Additional Module Control 6.3.3. Boot ROM Code 6.3.4. FPGA Interface Enables 6.3.5. ECC and Parity Control 6.3.6. Preloader Handoff Information 6.3.7. Clocks 6.3.8. Resets
6.3.2. Additional Module Control x
6.3.2.1. DMA Controller 6.3.2.2. NAND Flash Controller 6.3.2.3. CAN Controller 6.3.2.4. EMAC 6.3.2.5. USB 2.0 OTG Controller 6.3.2.6. SD/MMC Controller 6.3.2.7. Watchdog Timer
6.3.3. Boot ROM Code x
6.3.3.1. L3 Interconnect
7. Scan Manager x
7.1. Features of the Scan Manager 7.2. Scan Manager Block Diagram and System Integration 7.3. Functional Description of the Scan Manager 7.4. Scan Manager Address Map and Register Definitions
7.2. Scan Manager Block Diagram and System Integration x
7.2.1. Arm* JTAG-AP Signal Use in the Scan Manager 7.2.2. Arm* JTAG-AP Scan Chains
7.3. Functional Description of the Scan Manager x
7.3.1. Configuring HPS I/O Scan Chains 7.3.2. Communicating with the JTAG TAP Controller 7.3.3. JTAG-AP FIFO Buffer Access and Byte Command Protocol 7.3.4. Clocks 7.3.5. Resets
7.4. Scan Manager Address Map and Register Definitions x
7.4.1. JTAG-AP Register Name Cross Reference Table
8. System Interconnect x
8.1. Features of the System Interconnect 8.2. System Interconnect Block Diagram and System Integration 8.3. Functional Description of the Interconnect 8.4. System Interconnect Address Map and Register Definitions
8.2. System Interconnect Block Diagram and System Integration x
8.2.1. Interconnect Block Diagram 8.2.2. System Interconnect Architecture 8.2.3. Main Connectivity Matrix
8.3. Functional Description of the Interconnect x
8.3.1. Master to Slave Connectivity Matrix 8.3.2. System Interconnect Address Spaces 8.3.3. Master Caching and Buffering Overrides 8.3.4. Security 8.3.5. Configuring the Quality of Service Logic 8.3.6. Cyclic Dependency Avoidance Schemes 8.3.7. System Interconnect Master Properties 8.3.8. Interconnect Slave Properties 8.3.9. Upsizing Data Width Function 8.3.10. Downsizing Data Width Function 8.3.11. Lock Support 8.3.12. FIFO Buffers and Clock Crossing 8.3.13. System Interconnect Resets
8.3.2. System Interconnect Address Spaces x
8.3.2.1. Available Address Maps 8.3.2.2. L3 Address Space 8.3.2.3. MPU Address Space 8.3.2.4. SDRAM Address Space 8.3.2.5. Address Remapping
8.3.2.5. Address Remapping x
8.3.2.5.1. Bit Fields for Modifying the Memory Map
8.3.4. Security x
8.3.4.1. Slave Security 8.3.4.2. Master Security
8.3.6. Cyclic Dependency Avoidance Schemes x
8.3.6.1. Single Slave 8.3.6.2. Single Slave Per ID 8.3.6.3. Single Active Slave
8.3.9. Upsizing Data Width Function x
8.3.9.1. Incrementing Bursts 8.3.9.2. Wrapping Bursts 8.3.9.3. Fixed Bursts 8.3.9.4. Bypass Merge
8.3.10. Downsizing Data Width Function x
8.3.10.1. Incrementing Bursts 8.3.10.2. Wrapping Bursts 8.3.10.3. Fixed Bursts 8.3.10.4. Bypass Merge
8.3.12. FIFO Buffers and Clock Crossing x
8.3.12.1. Data Release Mechanism
9. HPS-FPGA Bridges x
9.1. Features of the HPS-FPGA Bridges 9.2. HPS-FPGA Bridges Block Diagram and System Integration 9.3. Functional Description of the HPS-FPGA Bridges 9.4. HPS-FPGA Bridges Address Map and Register Definitions
9.3. Functional Description of the HPS-FPGA Bridges x
9.3.1. The Global Programmers View 9.3.2. Functional Description of the FPGA-to-HPS Bridge 9.3.3. Functional Description of the HPS-to-FPGA Bridge 9.3.4. Functional Description of the Lightweight HPS-to-FPGA Bridge 9.3.5. Clocks and Resets 9.3.6. Data Width Sizing
9.3.2. Functional Description of the FPGA-to-HPS Bridge x
9.3.2.1. FPGA-to-HPS Access to ACP 9.3.2.2. FPGA-to-HPS Bridge Slave Signals
9.3.3. Functional Description of the HPS-to-FPGA Bridge x
9.3.3.1. HPS-to-FPGA Bridge Master Signals
9.3.4. Functional Description of the Lightweight HPS-to-FPGA Bridge x
9.3.4.1. Lightweight HPS-to-FPGA Bridge Master Signals
9.3.5. Clocks and Resets x
9.3.5.1. FPGA-to-HPS Bridge Clocks and Resets 9.3.5.2. HPS-to-FPGA Bridge Clocks and Resets 9.3.5.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets 9.3.5.4. Taking HPS-FPGA Bridges Out of Reset 9.3.5.5. GPV Clocks
10. Cortex®-A9 Microprocessor Unit Subsystem x
10.1. Features of the Cortex-A9 MPU Subsystem 10.2. Cortex®-A9 MPU Subsystem Block Diagram and System Integration 10.3. Cortex®-A9 MPCore 10.4. ACP ID Mapper 10.5. L2 Cache 10.6. CPU Prefetch 10.7. Debugging Modules 10.8. Clocks 10.9. Cortex®-A9 MPU Subsystem Register Implementation
10.2. Cortex®-A9 MPU Subsystem Block Diagram and System Integration x
10.2.1. Cortex®-A9 MPU Subsystem with System Interconnect 10.2.2. Cortex®-A9 MPU Subsystem Internals
10.3. Cortex®-A9 MPCore x
10.3.1. Functional Description 10.3.2. Implementation Details 10.3.3. Cortex®-A9 Processor 10.3.4. Interactive Debugging Features 10.3.5. L1 Caches 10.3.6. Preload Engine 10.3.7. Floating Point Unit 10.3.8. NEON* Multimedia Processing Engine 10.3.9. Memory Management Unit 10.3.10. Performance Monitoring Unit 10.3.11. Arm* Cortex* -A9 MPCore Timers 10.3.12. Generic Interrupt Controller 10.3.13. Global Timer 10.3.14. Snoop Control Unit 10.3.15. Accelerator Coherency Port
10.3.3. Cortex®-A9 Processor x
10.3.3.1. Reset
10.3.5. L1 Caches x
10.3.5.1. Cache Latency
10.3.8. NEON* Multimedia Processing Engine x
10.3.8.1. Single Instruction, Multiple Data (SIMD) Processing 10.3.8.2. Features of the NEON* MPE
10.3.9. Memory Management Unit x
10.3.9.1. TLBs Supported By the MMU 10.3.9.2. TLB Features 10.3.9.3. The Boot Region 10.3.9.4. The SDRAM Region 10.3.9.5. The FPGA Slaves Region 10.3.9.6. The HPS Peripherals Region
10.3.9.3. The Boot Region x
10.3.9.3.1. Boot ROM Mapping
10.3.11. Arm* Cortex* -A9 MPCore Timers x
10.3.11.1. Functional Description 10.3.11.2. Implementation Details
10.3.12. Generic Interrupt Controller x
10.3.12.1. Functional Description 10.3.12.2. Implementation Details
10.3.12.2. Implementation Details x
10.3.12.2.1. GIC Interrupt Map for the Cyclone V SoC HPS
10.3.13. Global Timer x
10.3.13.1. Functional Description 10.3.13.2. Implementation Details
10.3.14. Snoop Control Unit x
10.3.14.1. Functional Description 10.3.14.2. Implementation Details
10.3.14.1. Functional Description x
10.3.14.1.1. Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port
10.3.15. Accelerator Coherency Port x
10.3.15.1. AxUSER and AxCACHE Attributes 10.3.15.2. Cache Coherency for ACP Shared Requests 10.3.15.3. AXI Master Configuration for ACP Access 10.3.15.4. Burst Sizes and Byte Strobes 10.3.15.5. Exclusive and Locked Accesses 10.3.15.6. Avoiding ACP Dependency Lockup
10.3.15.3. AXI Master Configuration for ACP Access x
10.3.15.3.1. Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses 10.3.15.3.2. Configuring AxUSER[4:0] Sideband Signals 10.3.15.3.3. Configuring AxPROT[2:0] Sideband Signals for Coherent Accesses
10.3.15.4. Burst Sizes and Byte Strobes x
10.3.15.4.1. Recommended Burst Types
10.4. ACP ID Mapper x
10.4.1. Functional Description 10.4.2. Implementation Details 10.4.3. ACP ID Mapper Address Map and Register Definitions
10.4.2. Implementation Details x
10.4.2.1. ID Intended Usage 10.4.2.2. AXI User Sideband Override 10.4.2.3. Transaction Capabilities 10.4.2.4. Dynamic Mapping Mode 10.4.2.5. Fixed Mapping Mode 10.4.2.6. Control of the AXI User Sideband Signals 10.4.2.7. Memory Region Remap
10.4.2.5. Fixed Mapping Mode x
10.4.2.5.1. HPS Peripheral Master Input IDs
10.5. L2 Cache x
10.5.1. Functional Description
10.5.1. Functional Description x
10.5.1.1. Cache Controller Configuration 10.5.1.2. Single Event Upset Protection 10.5.1.3. L2 Cache Parity 10.5.1.4. L2 Cache Lockdown Capabilities 10.5.1.5. L2 Cache Event Monitoring 10.5.1.6. L2 Cache Address Filtering 10.5.1.7. Cache Latency
10.5.1.1. Cache Controller Configuration x
10.5.1.1.1. Implementation Details
10.5.1.1.1. Implementation Details x
10.5.1.1.1.1. L2 Cache Event Monitoring
10.7. Debugging Modules x
10.7.1. Program Trace 10.7.2. Event Trace 10.7.3. Cross-Triggering
10.9. Cortex®-A9 MPU Subsystem Register Implementation x
10.9.1. Cortex-A9 MPU Subsystem Address Map 10.9.2. L2 Cache Controller Address Map
11. CoreSight* Debug and Trace x
11.1. Features of CoreSight* Debug and Trace 11.2. Arm* CoreSight* Documentation 11.3. CoreSight Debug and Trace Block Diagram and System Integration 11.4. Functional Description of CoreSight Debug and Trace 11.5. CoreSight* Debug and Trace Programming Model 11.6. CoreSight Debug and Trace Address Map and Register Definitions
11.4. Functional Description of CoreSight Debug and Trace x
11.4.1. Debug Access Port 11.4.2. System Trace Macrocell 11.4.3. Trace Funnel 11.4.4. CoreSight Trace Memory Controller 11.4.5. AMBA* Trace Bus Replicator 11.4.6. Trace Port Interface Unit 11.4.7. Embedded Cross Trigger System 11.4.8. Program Trace Macrocell 11.4.9. HPS Debug APB* Interface 11.4.10. FPGA Interface 11.4.11. Debug Clocks 11.4.12. Debug Resets
11.4.4. CoreSight Trace Memory Controller x
11.4.4.1. Embedded Trace FIFO 11.4.4.2. Embedded Trace Router
11.4.7. Embedded Cross Trigger System x
11.4.7.1. Cross Trigger Interface 11.4.7.2. Cross Trigger Matrix
11.4.10. FPGA Interface x
11.4.10.1. DAP 11.4.10.2. STM 11.4.10.3. FPGA-CTI 11.4.10.4. TPIU
11.5. CoreSight* Debug and Trace Programming Model x
11.5.1. Coresight Component Address 11.5.2. STM Channels 11.5.3. CTI Trigger Connections to Outside the Debug System 11.5.4. Configuring Embedded Cross-Trigger Connections
11.5.3. CTI Trigger Connections to Outside the Debug System x
11.5.3.1. csCTI 11.5.3.2. FPGA-CTI
11.5.4. Configuring Embedded Cross-Trigger Connections x
11.5.4.1. Configuring Trigger Input 0 11.5.4.2. Triggering a Flush of Trace Data to the TPIU 11.5.4.3. Triggering an STM message 11.5.4.4. Triggering a Breakpoint on CPU 1
12. SDRAM Controller Subsystem x
12.1. Features of the SDRAM Controller Subsystem 12.2. SDRAM Controller Subsystem Block Diagram 12.3. SDRAM Controller Memory Options 12.4. SDRAM Controller Subsystem Interfaces 12.5. Memory Controller Architecture 12.6. Functional Description of the SDRAM Controller Subsystem 12.7. SDRAM Power Management 12.8. DDR PHY 12.9. Clocks 12.10. Resets 12.11. Port Mappings 12.12. Initialization 12.13. SDRAM Controller Subsystem Programming Model 12.14. Debugging HPS SDRAM in the Preloader 12.15. SDRAM Controller Address Map and Register Definitions
12.4. SDRAM Controller Subsystem Interfaces x
12.4.1. MPU Subsystem Interface 12.4.2. L3 Interconnect Interface 12.4.3. CSR Interface 12.4.4. FPGA-to-HPS SDRAM Interface
12.5. Memory Controller Architecture x
12.5.1. Multi-Port Front End 12.5.2. Single-Port Controller
12.5.2. Single-Port Controller x
12.5.2.1. Command Generator 12.5.2.2. Timer Bank Pool 12.5.2.3. Arbiter 12.5.2.4. Rank Timer 12.5.2.5. Write Data Buffer 12.5.2.6. ECC Block 12.5.2.7. AFI Interface 12.5.2.8. CSR Interface
12.6. Functional Description of the SDRAM Controller Subsystem x
12.6.1. MPFE Operation Ordering 12.6.2. MPFE Multi-Port Arbitration 12.6.3. MPFE SDRAM Burst Scheduling 12.6.4. Single-Port Controller Operation
12.6.4. Single-Port Controller Operation x
12.6.4.1. Command and Data Reordering 12.6.4.2. Bank Policy 12.6.4.3. Write Combining 12.6.4.4. Burst Length Support 12.6.4.5. ECC 12.6.4.6. Interleaving Options 12.6.4.7. AXI-Exclusive Support 12.6.4.8. Memory Protection 12.6.4.9. Example of Configuration for TrustZone
12.6.4.5. ECC x
12.6.4.5.1. Byte Writes 12.6.4.5.2. ECC Write Backs 12.6.4.5.3. User Notification of ECC Errors
12.8. DDR PHY x
12.8.1. DDR Calibration
12.10. Resets x
12.10.1. Taking the SDRAM Controller Subsystem Out of Reset
12.12. Initialization x
12.12.1. FPGA-to-SDRAM Protocol Details
12.12.1. FPGA-to-SDRAM Protocol Details x
12.12.1.1. Avalon-MM Bidirectional Port 12.12.1.2. Avalon-MM Write-Only Port 12.12.1.3. Avalon-MM Read Port 12.12.1.4. AXI Port
12.13. SDRAM Controller Subsystem Programming Model x
12.13.1. HPS Memory Interface Architecture 12.13.2. HPS Memory Interface Configuration 12.13.3. HPS Memory Interface Simulation 12.13.4. Generating a Preloader Image for HPS with EMIF
12.13.4. Generating a Preloader Image for HPS with EMIF x
12.13.4.1. Creating a Project in Platform Designer (Standard) 12.13.4.2. Creating a Top-Level File and Adding Constraints
12.14. Debugging HPS SDRAM in the Preloader x
12.14.1. Enabling UART or Semihosting Printout 12.14.2. Enabling Simple Memory Test 12.14.3. Enabling the Debug Report 12.14.4. Writing a Predefined Data Pattern to SDRAM in the Preloader
12.14.3. Enabling the Debug Report x
12.14.3.1. Analysis of Debug Report
13. On-Chip Memory x
13.1. On-Chip RAM 13.2. Boot ROM 13.3. On-Chip Memory Address Map and Register Definitions
13.1. On-Chip RAM x
13.1.1. Features of the On-Chip RAM 13.1.2. On-Chip RAM Block Diagram and System Integration 13.1.3. Functional Description of the On-Chip RAM
13.1.3. Functional Description of the On-Chip RAM x
13.1.3.1. On-Chip RAM Clocks 13.1.3.2. On-Chip RAM Resets 13.1.3.3. On-Chip RAM Initialization
13.2. Boot ROM x
13.2.1. Features of the Boot ROM 13.2.2. Boot ROM Block Diagram and System Integration 13.2.3. Functional Description of the Boot ROM
13.2.3. Functional Description of the Boot ROM x
13.2.3.1. Boot ROM Clocks 13.2.3.2. Boot ROM Resets
14. NAND Flash Controller x
14.1. NAND Flash Controller Features 14.2. NAND Flash Controller Block Diagram and System Integration 14.3. NAND Flash Controller Signal Descriptions 14.4. Functional Description of the NAND Flash Controller 14.5. NAND Flash Controller Programming Model 14.6. NAND Flash Controller Address Map and Register Definitions
14.4. Functional Description of the NAND Flash Controller x
14.4.1. Discovery and Initialization 14.4.2. Bootstrap Interface 14.4.3. Configuration by Host 14.4.4. Local Memory Buffer 14.4.5. Clocks 14.4.6. Resets 14.4.7. Indexed Addressing 14.4.8. Command Mapping 14.4.9. Data DMA 14.4.10. ECC
14.4.2. Bootstrap Interface x
14.4.2.1. Bootstrap Setting Bits
14.4.3. Configuration by Host x
14.4.3.1. Recommended Bootstrap Settings for 512-Byte Page Device 14.4.3.2. NAND Page Main and Spare Areas
14.4.5. Clocks x
14.4.5.1. Clock Generation 14.4.5.2. Clock Enable 14.4.5.3. Clock Switching
14.4.6. Resets x
14.4.6.1. Taking the NAND Flash Controller Out of Reset
14.4.7. Indexed Addressing x
14.4.7.1. Register Map for Indexed Addressing 14.4.7.2. Indexed Addressing Host Usage
14.4.8. Command Mapping x
14.4.8.1. MAP00 Commands 14.4.8.2. MAP01 Commands 14.4.8.3. MAP10 Commands 14.4.8.4. MAP11 Commands
14.4.8.1. MAP00 Commands x
14.4.8.1.1. MAP00 Command Format 14.4.8.1.2. MAP00 Usage Limitations
14.4.8.2. MAP01 Commands x
14.4.8.2.1. MAP01 Command Format 14.4.8.2.2. MAP01 Usage Limitations
14.4.8.3. MAP10 Commands x
14.4.8.3.1. MAP10 Command Format 14.4.8.3.2. MAP10 Operations 14.4.8.3.3. MAP10 Usage Limitations
14.4.8.4. MAP11 Commands x
14.4.8.4.1. MAP11 Control Format 14.4.8.4.2. MAP11 Usage Limitations
14.4.9. Data DMA x
14.4.9.1. Multi-Transaction DMA Command 14.4.9.2. Burst DMA Command
14.4.9.1. Multi-Transaction DMA Command x
14.4.9.1.1. Command-Data Pair Formats 14.4.9.1.2. Using Multi-Transaction DMA Commands
14.4.10. ECC x
14.4.10.1. Correction Capability, Sector Size, and Check Bit Size 14.4.10.2. ECC Programming Modes 14.4.10.3. Preserving Bad Block Markers 14.4.10.4. Error Correction Status
14.4.10.2. ECC Programming Modes x
14.4.10.2.1. Main Area Transfer Mode 14.4.10.2.2. Spare Area Transfer Mode 14.4.10.2.3. Main+Spare Area Transfer Mode
15. SD/MMC Controller x
15.1. Features of the SD/MMC Controller 15.2. SD/MMC Controller Block Diagram and System Integration 15.3. SD/MMC Controller Signal Description 15.4. Functional Description of the SD/MMC Controller 15.5. SD/MMC Controller Programming Model 15.6. SD/MMC Controller Address Map and Register Definitions
15.1. Features of the SD/MMC Controller x
15.1.1. SD Card Support Matrix 15.1.2. MMC Support Matrix
16. Quad SPI Flash Controller x
16.1. Features of the Quad SPI Flash Controller 16.2. Quad SPI Flash Controller Block Diagram and System Integration 16.3. Interface Signals 16.4. Functional Description of the Quad SPI Flash Controller 16.5. Quad SPI Flash Controller Programming Model 16.6. Quad SPI Flash Controller Address Map and Register Definitions
16.4. Functional Description of the Quad SPI Flash Controller x
16.4.1. Overview 16.4.2. Data Slave Interface 16.4.3. SPI Legacy Mode 16.4.4. Register Slave Interface 16.4.5. Local Memory Buffer 16.4.6. DMA Peripheral Request Controller 16.4.7. Arbitration between Direct/Indirect Access Controller and STIG 16.4.8. Configuring the Flash Device 16.4.9. XIP Mode 16.4.10. Write Protection 16.4.11. Data Slave Sequential Access Detection 16.4.12. Clocks 16.4.13. Resets 16.4.14. Interrupts
16.4.2. Data Slave Interface x
16.4.2.1. Direct Access Mode 16.4.2.2. Indirect Access Mode
16.4.2.1. Direct Access Mode x
16.4.2.1.1. Data Slave Remapping Example 16.4.2.1.2. AHB*
16.4.2.2. Indirect Access Mode x
16.4.2.2.1. Indirect Read Operation 16.4.2.2.2. Indirect Write Operation 16.4.2.2.3. Consecutive Reads and Writes
16.4.4. Register Slave Interface x
16.4.4.1. STIG Operation
16.4.8. Configuring the Flash Device x
16.4.8.1. Write Request
16.4.13. Resets x
16.4.13.1. Taking the Quad SPI Flash Controller Out of Reset 16.4.13.2. SRAM Initialization Procedure with ECC Enabled
16.5. Quad SPI Flash Controller Programming Model x
16.5.1. Setting Up the Quad SPI Flash Controller 16.5.2. Indirect Read Operation with DMA Disabled 16.5.3. Indirect Read Operation with DMA Enabled 16.5.4. Indirect Write Operation with DMA Disabled 16.5.5. Indirect Write Operation with DMA Enabled 16.5.6. XIP Mode Operations
16.5.6. XIP Mode Operations x
16.5.6.1. Entering XIP Mode 16.5.6.2. Exiting XIP Mode 16.5.6.3. XIP Mode at Power on Reset
16.5.6.1. Entering XIP Mode x
16.5.6.1.1. Micron Quad SPI Flash Devices with Support for Basic-XIP 16.5.6.1.2. Micron Quad SPI Flash Devices without Support for Basic-XIP 16.5.6.1.3. Winbond Quad SPI Flash Devices 16.5.6.1.4. Spansion Quad SPI Flash Devices
17. DMA Controller x
17.1. Features of the DMA Controller 17.2. DMA Controller Block Diagram and System Integration 17.3. Functional Description of the DMA Controller 17.4. DMA Controller Address Map and Register Definitions
17.3. Functional Description of the DMA Controller x
17.3.1. Peripheral Request Interface
17.3.1. Peripheral Request Interface x
17.3.1.1. Peripheral Request Interface Mapping
17.4. DMA Controller Address Map and Register Definitions x
17.4.1. Address Map and Register Definitions
18. Ethernet Media Access Controller x
18.1. Features of the Ethernet MAC 18.2. EMAC Block Diagram and System Integration 18.3. EMAC Signal Description 18.4. EMAC Internal Interfaces 18.5. Functional Description of the EMAC 18.6. Ethernet MAC Programming Model 18.7. Ethernet MAC Address Map and Register Definitions
18.1. Features of the Ethernet MAC x
18.1.1. MAC 18.1.2. DMA 18.1.3. Management Interface 18.1.4. Acceleration 18.1.5. PHY Interface
18.3. EMAC Signal Description x
18.3.1. HPS EMAC I/O Signals 18.3.2. FPGA EMAC I/O Signals 18.3.3. PHY Management Interface
18.3.3. PHY Management Interface x
18.3.3.1. MDIO Interface 18.3.3.2. I2C External PHY Management Interface
18.4. EMAC Internal Interfaces x
18.4.1. DMA Master Interface 18.4.2. Timestamp Interface
18.6. Ethernet MAC Programming Model x
18.6.1. System Level EMAC Configuration Registers 18.6.2. EMAC FPGA Interface Initialization 18.6.3. EMAC HPS Interface Initialization 18.6.4. DMA Initialization 18.6.5. EMAC Initialization and Configuration 18.6.6. Performing Normal Receive and Transmit Operation 18.6.7. Stopping and Starting Transmission 18.6.8. Programming Guidelines for Energy Efficient Ethernet 18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
18.6.8. Programming Guidelines for Energy Efficient Ethernet x
18.6.8.1. Entering and Exiting the TX LPI Mode 18.6.8.2. Gating Off the CSR Clock in the LPI Mode
18.6.8.2. Gating Off the CSR Clock in the LPI Mode x
18.6.8.2.1. Gating Off the CSR Clock in the RX LPI Mode 18.6.8.2.2. Gating Off the CSR Clock in the TX LPI Mode
18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output x
18.6.9.1. Generating a Single Pulse on PPS 18.6.9.2. Generating a Pulse Train on PPS 18.6.9.3. Generating an Interrupt without Affecting the PPS
19. USB 2.0 OTG Controller x
19.1. Features of the USB OTG Controller 19.2. USB OTG Controller Block Diagram and System Integration 19.3. USB 2.0 ULPI PHY Signal Description 19.4. Functional Description of the USB OTG Controller 19.5. USB OTG Controller Programming Model 19.6. USB 2.0 OTG Controller Address Map and Register Definitions
19.1. Features of the USB OTG Controller x
19.1.1. Supported PHYS
19.4. Functional Description of the USB OTG Controller x
19.4.1. USB OTG Controller Block Description 19.4.2. Local Memory Buffer 19.4.3. Clocks 19.4.4. Resets 19.4.5. Interrupts
19.4.1. USB OTG Controller Block Description x
19.4.1.1. Master Interface 19.4.1.2. Slave Interface 19.4.1.3. Application Interface Unit 19.4.1.4. Packet FIFO Controller 19.4.1.5. SPRAM 19.4.1.6. MAC 19.4.1.7. Wakeup and Power Control 19.4.1.8. PHY Interface Unit 19.4.1.9. DMA
19.4.1.2. Slave Interface x
19.4.1.2.1. Slave Interface CSR Unit
19.4.1.6. MAC x
19.4.1.6.1. USB Transactions 19.4.1.6.2. Host Protocol 19.4.1.6.3. Device Protocol 19.4.1.6.4. OTG Protocol
19.4.4. Resets x
19.4.4.1. Reset Requirements 19.4.4.2. Hardware Reset 19.4.4.3. Software Reset 19.4.4.4. Taking the USB 2.0 OTG Controller Out of Reset
19.5. USB OTG Controller Programming Model x
19.5.1. Enabling ECC 19.5.2. Enabling SPRAM ECCs 19.5.3. Host Operation 19.5.4. Device Operation
19.5.3. Host Operation x
19.5.3.1. Host Initialization 19.5.3.2. Host Transaction
19.5.4. Device Operation x
19.5.4.1. Device Initialization 19.5.4.2. Device Transaction
19.5.4.2. Device Transaction x
19.5.4.2.1. IN Transactions 19.5.4.2.2. OUT Transactions 19.5.4.2.3. Control Transfers
19.6. USB 2.0 OTG Controller Address Map and Register Definitions x
19.6.131.1.1. USB OTG Controller Module Registers Address Map19.6.131.1.1. USB OTG Controller Module Registers Address Map
19.6.131.1.1. USB OTG Controller Module Registers Address Map19.6.131.1.1. USB OTG Controller Module Registers Address Map x
19.6.1.1. USB Data FIFO Address Map 19.6.1.2. USB Direct Access FIFO RAM Address Map
20. SPI Controller x
20.1. Features of the SPI Controller 20.2. SPI Block Diagram and System Integration 20.3. SPI Controller Signal Description 20.4. Functional Description of the SPI Controller 20.5. SPI Programming Model 20.6. SPI Controller Address Map and Register Definitions
20.2. SPI Block Diagram and System Integration x
20.2.1. SPI Block Diagram
20.3. SPI Controller Signal Description x
20.3.1. Interface to HPS I/O 20.3.2. FPGA Routing
20.4. Functional Description of the SPI Controller x
20.4.1. Protocol Details and Standards Compliance 20.4.2. SPI Controller Overview 20.4.3. Transfer Modes 20.4.4. SPI Master 20.4.5. SPI Slave 20.4.6. Partner Connection Interfaces 20.4.7. DMA Controller Interface 20.4.8. Slave Interface 20.4.9. Clocks and Resets
20.4.2. SPI Controller Overview x
20.4.2.1. Serial Bit-Rate Clocks 20.4.2.2. Transmit and Receive FIFO Buffers 20.4.2.3. SPI Interrupts
20.4.2.1. Serial Bit-Rate Clocks x
20.4.2.1.1. SPI Master Bit-Rate Clock 20.4.2.1.2. SPI Slave Bit-Rate Clock
20.4.3. Transfer Modes x
20.4.3.1. Transmit and Receive 20.4.3.2. Transmit Only 20.4.3.3. Receive Only 20.4.3.4. EEPROM Read
20.4.4. SPI Master x
20.4.4.1. RXD Sample Delay 20.4.4.2. Data Transfers 20.4.4.3. Master SPI and SSP Serial Transfers 20.4.4.4. Master Microwire Serial Transfers
20.4.5. SPI Slave x
20.4.5.1. Slave SPI and SSP Serial Transfers  20.4.5.2. Serial Transfers 20.4.5.3. Glue Logic for Master Port ss_in_n
20.4.6. Partner Connection Interfaces x
20.4.6.1. Motorola SPI Protocol 20.4.6.2. Texas Instruments Synchronous Serial Protocol (SSP) 20.4.6.3. National Semiconductor Microwire Protocol
20.4.8. Slave Interface x
20.4.8.1. Control and Status Register Access 20.4.8.2. Data Register Access
20.4.9. Clocks and Resets x
20.4.9.1. Taking the SPI Controller Out of Reset
20.5. SPI Programming Model x
20.5.1. Master SPI and SSP Serial Transfers 20.5.2. Master Microwire Serial Transfers 20.5.3. Slave SPI and SSP Serial Transfers 20.5.4. Slave Microwire Serial Transfers 20.5.5. Software Control for Slave Selection 20.5.6. DMA Controller Operation
20.5.5. Software Control for Slave Selection x
20.5.5.1. Example: Slave Selection Software Flow for SPI Master 20.5.5.2. Example: Slave Selection Software Flow for SPI Slave
20.5.6. DMA Controller Operation x
20.5.6.1. Transmit FIFO Buffer Underflow 20.5.6.2. Transmit FIFO Watermark 20.5.6.3. Transmit FIFO Buffer Overflow 20.5.6.4. Receive FIFO Buffer Overflow 20.5.6.5. Choosing Receive Watermark Level 20.5.6.6. Receive FIFO Buffer Underflow
20.5.6.2. Transmit FIFO Watermark x
20.5.6.2.1. Example 1: Transmit FIFO Watermark Level = 64 20.5.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
21. I2C Controller x
21.1. Features of the I2C Controller 21.2. I2C Controller Block Diagram and System Integration 21.3. I2C Controller Signal Description 21.4. Functional Description of the I2C Controller 21.5. I2C Controller Programming Model 21.6. I2C Controller Address Map and Register Definitions
21.4. Functional Description of the I2C Controller x
21.4.1. Feature Usage 21.4.2. Behavior 21.4.3. Protocol Details 21.4.4. Multiple Master Arbitration 21.4.5. Clock Frequency Configuration 21.4.6. SDA Hold Time 21.4.7. DMA Controller Interface 21.4.8. Clocks 21.4.9. Resets
21.4.2. Behavior x
21.4.2.1. START and STOP Generation 21.4.2.2. Combined Formats
21.4.3. Protocol Details x
21.4.3.1. START and STOP Conditions 21.4.3.2. Addressing Slave Protocol 21.4.3.3. Transmitting and Receiving Protocol 21.4.3.4. START BYTE Transfer Protocol
21.4.3.2. Addressing Slave Protocol x
21.4.3.2.1. 7-Bit Address Format 21.4.3.2.2. 10-Bit Address Format
21.4.3.3. Transmitting and Receiving Protocol x
21.4.3.3.1. Master-Transmitter and Slave-Receiver 21.4.3.3.2. Master-Receiver and Slave-Transmitter
21.4.4. Multiple Master Arbitration x
21.4.4.1. Clock Synchronization
21.4.5. Clock Frequency Configuration x
21.4.5.1. Minimum High and Low Counts
21.4.5.1. Minimum High and Low Counts x
21.4.5.1.1. Calculating High and Low Counts
21.4.9. Resets x
21.4.9.1. Taking the I2C Controller Out of Reset
21.5. I2C Controller Programming Model x
21.5.1. Slave Mode Operation 21.5.2. Master Mode Operation 21.5.3. Disabling the I2C Controller 21.5.4. DMA Controller Operation
21.5.1. Slave Mode Operation x
21.5.1.1. Initial Configuration 21.5.1.2. Slave-Transmitter Operation for a Single Byte 21.5.1.3. Slave-Receiver Operation for a Single Byte 21.5.1.4. Slave-Transfer Operation for Bulk Transfers
21.5.2. Master Mode Operation x
21.5.2.1. Initial Configuration 21.5.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update 21.5.2.3. Master Transmit and Master Receive
21.5.4. DMA Controller Operation x
21.5.4.1. Transmit FIFO Underflow 21.5.4.2. Transmit Watermark Level 21.5.4.3. Transmit FIFO Overflow 21.5.4.4. Receive FIFO Overflow 21.5.4.5. Receive Watermark Level 21.5.4.6. Receive FIFO Underflow
22. UART Controller x
22.1. UART Controller Features 22.2. UART Controller Block Diagram and System Integration 22.3. UART Controller Signal Description 22.4. Functional Description of the UART Controller 22.5. DMA Controller Operation 22.6. UART Controller Address Map and Register Definitions
22.3. UART Controller Signal Description x
22.3.1. HPS I/O Pins 22.3.2. FPGA Routing
22.4. Functional Description of the UART Controller x
22.4.1. FIFO Buffer Support 22.4.2. UART(RS232) Serial Protocol 22.4.3. Automatic Flow Control 22.4.4. Clocks 22.4.5. Resets 22.4.6. Interrupts
22.4.3. Automatic Flow Control x
22.4.3.1. Automatic RTS mode 22.4.3.2. Automatic CTS mode
22.4.5. Resets x
22.4.5.1. Taking the UART Controller Out of Reset
22.4.6. Interrupts x
22.4.6.1. Programmable THRE Interrupt
22.5. DMA Controller Operation x
22.5.1. Transmit FIFO Underflow 22.5.2. Transmit Watermark Level 22.5.3. Transmit FIFO Overflow 22.5.4. Receive FIFO Overflow 22.5.5. Receive Watermark Level 22.5.6. Receive FIFO Underflow
22.5.2. Transmit Watermark Level x
22.5.2.1. IIR_FCR.TET = 1 22.5.2.2. IIR_FCR.TET = 3
23. General-Purpose I/O Interface x
23.1. Features of the GPIO Interface 23.2. GPIO Interface Block Diagram and System Integration 23.3. Functional Description of the GPIO Interface 23.4. GPIO Interface Programming Model 23.5. General-Purpose I/O Interface Address Map and Register Definitions
23.3. Functional Description of the GPIO Interface x
23.3.1. Debounce Operation 23.3.2. Pin Directions 23.3.3. Taking the GPIO Interface Out of Reset 23.3.4. GPIO Pin State During Reset
24. Timer x
24.1. Features of the Timer 24.2. Timer Block Diagram and System Integration 24.3. Functional Description of the Timer 24.4. Timer Programming Model 24.5. Timer Address Map and Register Definitions
24.3. Functional Description of the Timer x
24.3.1. Clocks 24.3.2. Resets 24.3.3. Interrupts 24.3.4. FPGA Interface
24.4. Timer Programming Model x
24.4.1. Initialization 24.4.2. Enabling the Timer 24.4.3. Disabling the Timer 24.4.4. Loading the Timer Countdown Value 24.4.5. Servicing Interrupts
24.4.5. Servicing Interrupts x
24.4.5.1. Clearing the Interrupt 24.4.5.2. Checking the Interrupt Status 24.4.5.3. Masking the Interrupt
25. Watchdog Timer x
25.1. Features of the Watchdog Timer 25.2. Watchdog Timer Block Diagram and System Integration 25.3. Functional Description of the Watchdog Timer 25.4. Watchdog Timer Programming Model 25.5. Watchdog Timer Address Map and Register Definitions
25.3. Functional Description of the Watchdog Timer x
25.3.1. Watchdog Timer Counter 25.3.2. Watchdog Timer Pause Mode 25.3.3. Watchdog Timer Clocks 25.3.4. Watchdog Timer Resets 25.3.5. FPGA Interface
25.3.4. Watchdog Timer Resets x
25.3.4.1. Taking the Watchdog Timer Out of Reset
25.4. Watchdog Timer Programming Model x
25.4.1. Setting the Timeout Period Values 25.4.2. Selecting the Output Response Mode 25.4.3. Enabling and Initially Starting a Watchdog Timer 25.4.4. Reloading a Watchdog Counter 25.4.5. Pausing a Watchdog Timer 25.4.6. Disabling and Stopping a Watchdog Timer 25.4.7. Watchdog Timer State Machine
26. CAN Controller x
26.1. Features of the CAN Controller 26.2. CAN Controller Block Diagram and System Integration 26.3. Functional Description of the CAN Controller 26.4. CAN Controller Programming Model 26.5. CAN Controller Address Map and Register Definitions
26.3. Functional Description of the CAN Controller x
26.3.1. Message Object 26.3.2. Message Interface Registers 26.3.3. DMA Mode 26.3.4. Automatic Retransmission 26.3.5. Test Mode 26.3.6. L4 Slave Interface 26.3.7. Clocks 26.3.8. Software Reset 26.3.9. Hardware Reset 26.3.10. Interrupts
26.3.1. Message Object x
26.3.1.1. Message Object Control Flags 26.3.1.2. Message Object Mask Bits 26.3.1.3. CAN Message Bits
26.3.1.1. Message Object Control Flags x
26.3.1.1.1. Message Valid (MsgVal) 26.3.1.1.2. New Data (NewDat) 26.3.1.1.3. Message Lost (MsgLst) 26.3.1.1.4. Interrupt Pending (IntPnd) 26.3.1.1.5. Transmit Interrupt Enable (TxIE) 26.3.1.1.6. Receive Interrupt Enable (RxIE) 26.3.1.1.7. Remote Enable (RmtEn) 26.3.1.1.8. Transmit Request (TxRqst) 26.3.1.1.9. End of Block (EoB)
26.3.1.2. Message Object Mask Bits x
26.3.1.2.1. Use Acceptance Mask (UMask) 26.3.1.2.2. Identifier Mask (Msk[28:0]) 26.3.1.2.3. Extended Identifier Mask (MXtd) 26.3.1.2.4. Mask Message Direction (MDir)
26.3.1.3. CAN Message Bits x
26.3.1.3.1. Message Identifier (ID[28:0]) 26.3.1.3.2. Extended Frame Identifier (Xtd) 26.3.1.3.3. Message Direction (Dir) 26.3.1.3.4. Data Length Code (DLC[3:0]) 26.3.1.3.5. Data Bytes 0-7 (Data 0[7:0] - Data 7[7:0])
26.3.5. Test Mode x
26.3.5.1. Silent Mode 26.3.5.2. Loopback Mode 26.3.5.3. Combined Mode
26.3.9. Hardware Reset x
26.3.9.1. Taking the CAN Controller Out of Reset
26.3.10. Interrupts x
26.3.10.1. Error Interrupts 26.3.10.2. Status Interrupts 26.3.10.3. Message Object Interrupts
26.4. CAN Controller Programming Model x
26.4.1. Software Initialization 26.4.2. CAN Message Transfer 26.4.3. Message Object Reconfiguration for Frame Reception 26.4.4. Message Object Reconfiguration for Frame Transmission
27. Introduction to the HPS Component x
27.1. MPU Subsystem 27.2. Arm* CoreSight* Debug Components 27.3. Interconnect 27.4. HPS-to-FPGA Interfaces 27.5. Memory Controllers 27.6. Support Peripherals 27.7. Interface Peripherals 27.8. On-Chip Memories
28. Instantiating the HPS Component x
28.1. FPGA Interfaces 28.2. Configuring HPS Clocks and Resets 28.3. Configuring Peripheral Pin Multiplexing 28.4. Configuring the External Memory Interface 28.5. Using the Address Span Extender Component 28.6. Generating and Compiling the HPS Component
28.1. FPGA Interfaces x
28.1.1. General Interfaces 28.1.2. FPGA-to-HPS SDRAM Interface 28.1.3. DMA Peripheral Request 28.1.4. Interrupts 28.1.5. AXI Bridges
28.2. Configuring HPS Clocks and Resets x
28.2.1. User Clocks 28.2.2. Reset Interfaces 28.2.3. PLL Reference Clocks 28.2.4. Peripheral FPGA Clocks
28.2.1. User Clocks x
28.2.1.1. User Clock Parameters 28.2.1.2. Clock Frequency Usage
28.3. Configuring Peripheral Pin Multiplexing x
28.3.1. Configuring Peripherals 28.3.2. Connecting Unassigned Pins to GPIO 28.3.3. Using Unassigned IO as LoanIO 28.3.4. Resolving Pin Multiplexing Conflicts 28.3.5. Peripheral Signals Routed to FPGA
28.4. Configuring the External Memory Interface x
28.4.1. Selecting PLL Output Frequency and Phase
29. HPS Component Interfaces x
29.1. Memory-Mapped Interfaces 29.2. Clocks 29.3. Resets 29.4. Debug and Trace Interfaces 29.5. Peripheral Signal Interfaces 29.6. Other Interfaces
29.1. Memory-Mapped Interfaces x
29.1.1. FPGA-to-HPS Bridge 29.1.2. HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges 29.1.3. FPGA-to-HPS SDRAM Interface
29.1.1. FPGA-to-HPS Bridge x
29.1.1.1. ACP Sideband Signals
29.2. Clocks x
29.2.1. Alternative Clock Inputs to HPS PLLs 29.2.2. User Clocks 29.2.3. AXI Bridge FPGA Interface Clocks 29.2.4. SDRAM Clocks 29.2.5. Peripheral FPGA Clocks
29.3. Resets x
29.3.1. HPS-to-FPGA Reset Interfaces 29.3.2. HPS External Reset Request 29.3.3. Peripheral Reset Interfaces
29.4. Debug and Trace Interfaces x
29.4.1. Trace Port Interface Unit 29.4.2. FPGA System Trace Macrocell Events Interface 29.4.3. FPGA Cross Trigger Interface 29.4.4. Debug APB* Interface
29.5. Peripheral Signal Interfaces x
29.5.1. DMA Controller Interface
29.6. Other Interfaces x
29.6.1. MPU Standby and Event Interfaces 29.6.2. General Purpose Signals 29.6.3. FPGA-to-HPS Interrupts 29.6.4. Boot from FPGA Interface 29.6.5. Input-only General Purpose Interface
30. Simulating the HPS Component x
30.1. Simulation Flows 30.2. Clock and Reset Interfaces 30.3. FPGA-to-HPS AXI Slave Interface 30.4. HPS-to-FPGA AXI Master Interface 30.5. Lightweight HPS-to-FPGA AXI Master Interface 30.6. FPGA-to-HPS SDRAM Interface 30.7. HPS-to-FPGA MPU Event Interface 30.8. Interrupts Interface 30.9. HPS-to-FPGA Debug APB* Interface 30.10. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 30.11. HPS-to-FPGA Cross-Trigger Interface 30.12. HPS-to-FPGA Trace Port Interface 30.13. FPGA-to-HPS DMA Handshake Interface 30.14. Boot from FPGA Interface 30.15. General Purpose Input Interface
30.1. Simulation Flows x
30.1.1. Setting Up the HPS Component for Simulation 30.1.2. Generating the HPS Simulation Model in Platform Designer (Standard) 30.1.3. Running the Simulations
30.1.1. Setting Up the HPS Component for Simulation x
30.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
30.1.1.1. HPS Conduit Interfaces Connecting to the FPGA x
30.1.1.1.1. Setting Up the HPS Component for Simulation
30.1.3. Running the Simulations x
30.1.3.1. Running HPS RTL Simulation 30.1.3.2. Running HPS Post-Fit Simulation
30.1.3.2. Running HPS Post-Fit Simulation x
30.1.3.2.1. Post-Fit Simulation Files 30.1.3.2.2. BFM API Hierarchy Format
30.2. Clock and Reset Interfaces x
30.2.1. Clock Interface 30.2.2. Reset Interface
30.6. FPGA-to-HPS SDRAM Interface x
30.6.1. HPS Memory Interface Simulation
31. Register Address Map for Cyclone V HPS x
31.1. HPS
31.1. HPS x
19.6.131.1.1. USB OTG Controller Module Registers Address Map19.6.131.1.1. USB OTG Controller Module Registers Address Map
19.6.131.1.1. USB OTG Controller Module Registers Address Map19.6.131.1.1. USB OTG Controller Module Registers Address Map x
31.1.1.1. USB Data FIFO Address Map 31.1.1.2. USB Direct Access FIFO RAM Address Map
A. Booting and Configuration x
A.1. Boot Overview A.2. FPGA Configuration Overview A.3. Booting and Configuration Options A.4. Boot Definitions A.5. Boot ROM Flow A.6. Typical Preloader Boot Flow A.7. FPGA Configuration
A.4. Boot Definitions x
A.4.1. Reset A.4.2. Boot ROM A.4.3. Boot Select A.4.4. Flash Memory Devices for Booting A.4.5. Clock Select A.4.6. I/O Configuration A.4.7. L4 Watchdog 0 Timer A.4.8. Preloader A.4.9. U-Boot Loader
A.4.3. Boot Select x
A.4.3.1. Boot Source I/O Mapping
A.4.3.1. Boot Source I/O Mapping x
A.4.3.1.1. Boot Source I/O Configuration
A.4.4. Flash Memory Devices for Booting x
A.4.4.1. SD/MMC Flash Devices A.4.4.2. NAND Flash Devices A.4.4.3. Quad SPI Flash Devices
A.4.4.1. SD/MMC Flash Devices x
A.4.4.1.1. Default Settings of the SD/MMC Controller A.4.4.1.2. CSEL Settings for the SD/MMC Controller
A.4.4.2. NAND Flash Devices x
A.4.4.2.1. NAND Flash Driver Features Supported in the Boot ROM Code A.4.4.2.2. CSEL Settings for the NAND Controller
A.4.4.3. Quad SPI Flash Devices x
A.4.4.3.1. Quad SPI Controller Default Settings A.4.4.3.2. Quad SPI Flash Delay Configuration A.4.4.3.3. Quad SPI Controller CSEL Settings
A.6. Typical Preloader Boot Flow x
A.6.1. HPS State on Entry to the Preloader A.6.2. Shared Memory A.6.3. Loading the Preloader Image
A.7. FPGA Configuration x
A.7.1. Full Configuration A.7.2. Partial Reconfiguration
1. Cyclone® V Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Clock Manager
4. Reset Manager
5. FPGA Manager
6. System Manager
7. Scan Manager
8. System Interconnect
9. HPS-FPGA Bridges
10. Cortex®-A9 Microprocessor Unit Subsystem
11. CoreSight* Debug and Trace
12. SDRAM Controller Subsystem
13. On-Chip Memory
14. NAND Flash Controller
15. SD/MMC Controller
16. Quad SPI Flash Controller
17. DMA Controller
18. Ethernet Media Access Controller
19. USB 2.0 OTG Controller
20. SPI Controller
21. I2C Controller
22. UART Controller
23. General-Purpose I/O Interface
24. Timer
25. Watchdog Timer
26. CAN Controller
27. Introduction to the HPS Component
28. Instantiating the HPS Component
29. HPS Component Interfaces
30. Simulating the HPS Component
31. Register Address Map for Cyclone V HPS
A. Booting and Configuration

12.14.3.1. Analysis of Debug Report

The following analysis helps you interpret the debug report.

  • The Read Deskew and Write Deskew results shown in the debug report are before calibration. (Before calibration results are actually from the window seen during calibration, and are most useful for debugging.)
  • For each DQ group, the Write Deskew, Read Deskew, DM Deskew, and Read after Write results map to the before-calibration margins reported in the EMIF Debug Toolkit.
    Note: The Write Deskew, Read Deskew, DM Deskew, and Read after Write results are reported in delay steps (nominally 25ps, in Arria V and Cyclone V devices), not in picoseconds.
  • DQS Enable calibration is reported as a VFIFO setting (in one clock period steps), a phase tap (in one-eighth clock period steps), and a delay chain step (in 25ps steps). 
    SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Start  VFIFO  5 ; Phase 6 ; Delay  4
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; End    VFIFO  6 ; Phase 5 ; Delay  9
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Center VFIFO  6 ; Phase 2 ; Delay  1
    Analysis of DQS Enable results: A VFIFO tap is 1 clock period, a phase is 1/8 clock period (45 degrees) and delay is nominally 25ps per tap. The DQSen window is the difference between the start and end—for the above example, assuming a frequency of 400 MHz (2500ps), that calculates as follows: start is 5*2500 + 6*2500/8 +4*25 = 14475ps. By the same calculation, the end is 16788ps. Consequently, the DQSen window is 2313ps.
  • The size of a read window or write window is equal to (left edge + right edge) * delay chain step size. Both the left edge and the right edge can be negative or positive.: 
    SEQ.C: Read Deskew  ; DQ  0 ; Rank 0 ; Left edge  18 ; Right edge  27 ; DQ delay  0 ; DQS delay  8
SEQ.C: Write Deskew ; DQ  0 ; Rank 0 ; Left edge  30 ; Right edge  17 ; DQ delay  6 ; DQS delay  4
    Analysis of DQ and DQS delay results: The DQ and DQS output delay (write) is the D5 delay chain. The DQ input delay (read) is the D1 delay chain, the DQS input delay (read) is the D4 delay chain.
  • Consider the following example of latency results: 
    SEQ.C: LFIFO Calibration ; Latency 10
    Analysis of latency results: This is the calibrated PHY read latency. The EMIF Debug Toolkit does not report this figure. This latency is reported in clock cycles.
  • Consider the following example of FOM results: 
    SEQ.C: FOM IN  = 83
SEQ.C: FOM OUT = 91
    Analysis of FOM results: The FOM IN value is a measure of the health of the read interface; it is calculated as the sum over all groups of the minimum margin on DQ plus the margin on DQS, divided by 2. The FOM OUT is a measure of the health of the write interface; it is calculated as the sum over all groups of the minimum margin on DQ plus the margin on DQS, divided by 2. You may refer to these values as indicators of improvement when you are experimenting with various termination schemes, assuming there are no individual misbehaving DQ pins.
  • The debug report does not provide delay chain step size values. The delay chain step size varies with device speed grade. Refer to your device data sheet for exact incremental delay values for delay chains.
Related Information
Level Two Title