Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

18.1.2. DMA

  • 32‑bit interface
  • Programmable burst size for optimal bus utilization
  • Single-channel mode transmit and receive engines
  • Byte-aligned addressing mode for data buffer support
  • Dual-buffer (ring) or linked-list (chained) descriptor chaining
  • Descriptors can each transfer up to 8 KB of data
  • Independent DMA arbitration for transmit and receive with fixed priority or round robin