Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

14.4.9.1.1. Command-Data Pair Formats

Table 117.  Command-Data Pair 1
  31:28 27:26 25:24 23:<M> (<M> – 1):0
Command 0x0 0x2 0x0 Block address Page address
Note: <M> = ceil(log2(<device pages per block>)). Therefore, use the following values:
  • 32 pages per block: <M>=5
  • 64 pages per block: <M>=6
  • 128 pages per block: <M>=7
  • 256 pages per block: <M>=8
  • 384 pages per block: <M>=9
  • 512 pages per block: <M>=9
  31:16 15:12 11:8 7:0
Data 0x0 0x2

0x0 = Read

0x1 = Write

<PP>= Number of pages
Table 118.  Command-Data Pair 2
  31:28 27:26 25:24 23:8 7:0
Command 0x0 0x2 0x0 Memory address high 0x0
  31:16 15:12 11:8 7:0
Data 0x0 0x2 0x2 0x0
Table 119.  Command-Data Pair 3
  31:28 27:26 25:24 23:8 7:0
Command 0x0 0x2 0x0 Memory address low33 0x0
  31:16 15:12 11:8 7:0
Data 0x0 0x2 0x3 0x0
Table 120.  Command-Data Pair 4
  31:28 27:26 25:24 23:17 16 15:8 7:0
Command 0x0 0x2 0x0 0x0 INT34 Burst length35 0x0
Note: INT controls the value of the dma_cmd_comp bit of the intr_status0 register in the status group at the end of the DMA transfer. INT can take on one of the following values:
  • 0—Do not interrupt host. The dma_cmd_comp bit is set to 0.
  • 1—Interrupt host. The dma_cmd_comp bit is set to 1.
  31:16 15:12 11:8 7:0
Data 0x0 0x2 0x4 0x0
32 <M> depends on the number of pages per block in the device. For more information about <M>, see the Note at the bottom of this table.
33 The buffer address in host memory, which must be aligned to 32 bits.
34 INT specifies the host interrupt to be generated at the end of the complete DMA transfer. For more information about INT, see the Note at the bottom of this table.
35 Can be only 4, 16, 32, or 64 bytes. No other values are valid.