DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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14.5.5. Synthesis Information (SynthesisInfo)

Use the SynthesisInfo block to set the synthesis mode and label a primitive subsystem as the top-level synthesizable subsystem. DSP Builder flattens and synthesizes the subsystem, and all those subsystems below as a unit. Primitive subsystems must have a SynthesisInfo block. DSP Builder creates pipelines and redistributes memories optimally to achieve the desired clock frequency. The SynthesisInfo block controls the synthesis flow for the current model.

The inputs and outputs to this subsystem become the primary inputs and outputs of the RTL entity that DSP Builder creates.

The SynthesisInfo block can be at the same level as the Device block (if the synthesizable subsystem is the same as the generated hardware subsystem). However, it is often convenient to create a separate subsystem level that contains the Device block. Refer to the design examples for some examples of design hierarchy.

Table 262.  Parameters for the SynthesisInfo Block
Parameter Description
Constrain Latency This option allows you to select the type of constraint and to specify its value. The value can be a workspace variable or an expression but must evaluate to a positive integer.

You can select the following types of constraint:

  • >: Greater than
  • >=: Greater than or equal to
  • =: Equal to
  • <=: Less than or equal to
  • <: Less than

Select either + or - and type in a reference model in the text field. Specify the reference as a Simulink path string e.g. ‘design/topLevel/model’. DSP Builder then ensures the latency depends on that model, otherwise the default is that DSP Builder depends on no model.

Constrain Latency only applies to subsystems which use the ChannelIn or ChannelOut blocks and not to subsystems that use the GPIn or GPOut blocks.

Bit accurate simulation Turn on in floating-point designs to give bit accurate rather than mathematical simulations. Fixed point designs always use bit accurate.
Local reset minimization

Select the reset minimization for the associated synthesizable subsystem. Valid only if Control block Global Enable is On.

The default is Conditional – On for ChannelIn/Out only.

Select Off to disable reset minimization on this synthesizable subsystem.

Select On – Always (for ChannelIn/Out or GPIn/Out to apply reset minimization to a synthesizable subsystem that uses GPIn/Out blocks. In a GPIn/Out subsystem with reset minimization, the whole subsystem is data flow and has no valid signal to be control flow.

The SynthesisInfo block has no inputs or outputs.