DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
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3.7.3.1. Assigning Base Addresses in DSP Builder Designs

You can add or drop IP or Primitive library control register fields and memory into your design.

Procedure

  1. Record the base address of the modules that connect to the Avalon-MM interface.
  2. Start from address 0 in your design or any other arbitrary integer. The base address is a relative address and is expressed as an integer.
    The base address depends on the data width of the bus and the width of the parameterizable variables. For example, FIR coefficients, where a register for a 32-bit FIR coefficient requires two words on a 16-bit bus.
  3. Note the relative base addresses of modules within your design.
    When you integrate your model into a Platform Designer system, Platform Designer generates a base address for the entire DSP Builder model. Platform Designer references individual modules within the .mdl design based on the model base address (autogenerated) and relative base address you assign in the .mdl file or its setup script.
  4. Manage base addresses, by specifying the bus data width in the Control block.
  5. For IP designs consider the number of registers each IP core needs and the number of words each register requires
  6. For Primitive subsystems, treat registers independently.
  7. Ensure each IP library block and register or memory in a Primitive subsystem has a unique base address.