DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
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14.3.4. Butterfly I C (BFIC) (Deprecated)

The BFIC block implements the butterfly I functionality associated with the radix-22 fully streaming FFT architecture.

You should parameterize this block with the incoming data type to ensure that DSP Builder maintains the necessary data precision. At the output, DSP Builder applies an additional bit of growth.

The s port connects to the control logic. This control logic is the extraction of the appropriate bit of a modulo N counter. The value of s determines the signal routing of each sample and the mathematical combination with other samples.

Table 101.  Parameters for the BFIC Block
Parameter Description
Input bits Specifies the number of input bits.
Input scaling exponent Specifies the fixed-point scaling factor of the input.
Table 102.  Port Interface for the BFIC Block
Signal Direction Type Description
s Input Boolean or unsigned integer uint(1) Control pin.
x1 Input Complex fixed-point data-type determined by parameterization Complex data input from ComplexSampleDelay.
x2 Input Complex fixed-point data-type determined by parameterization Complex data input from previous stage.
z1 Output Complex fixed-point data-type determined by parameterization Complex data output to next stage.
z2 Output Complex fixed-point data-type determined by parameterization Complex data output to ComplexSampleDelay.