DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.7.13. Single-Precision Real Floating-Point Matrix Multiply

This design example is a simpler design example of a floating-point matrix multiply implementation than the complex multiply example. The design example uses many more multiply-adds in parallel (128 single precision multiply adds in the default parameterization), to perform each vector multiply simultaneously.

The model file is matmul_flash_RS.mdl.