DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.3.8. Dual Twiddle Memory (DualTwiddleMemoryC)

The DualTwiddleMemory block calculates the complex twiddle factors associated with the evaluation of exp(-2pi.k1/N) and exp(-2pi.k2/N).

This block uses an efficient dual-port architecture to minimize the size of the internal lookup table while supporting the generation of two complex twiddle factors per clock cycle. The block provides k1 and k2 at the input and they must be less than or equal to a synthesis time parameter N. Enter the width in bits and fixed-point scaling of the twiddle factors.

A cosine/sine wave has a range of [-1:1], so you must provide at least two integer bits, and as many fractional bits as are appropriate. A good starting point is a twiddle width in bits of 16 bits (enter 16 as the Precision), and a scaling of 2^-14 (enter 14 as the Scaling exponent). The resulting fixed-point type is sfix16_en14 (2.14 in fixed-point format).

Table 108.  Parameters for the DualTwiddleMemoryC Block
Parameter Description
Number of points (N) Specifies the number of points on the unit circle.
Precision Specifies the precision in bits of the twiddle factors.
Twiddle scaling exponent Specifies the fixed-point scaling factor of the complex twiddle factor.
Table 109.  Port Interface for the DualTwiddleMemoryC Block
Signal Direction Type Description
k1 Input Unsigned integer in range 0 to (N – 1) Desired twiddle factor index.
k2 Input Unsigned integer in range 0 to (N – 1) Desired twiddle factor index.
q1 Output Type determined by parameterization Twiddle factor 1 (complex).
q2 Output Type determined by parameterization Twiddle factor 2(complex).