DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
Public

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14.3.18. Pulse Multiplier (PulseMultiplier)

The PulseMultiplier block stretches a single-cycle pulse on its input into a 2^N-cycle pulse on its output. The block ignores any input pulse that arrives within 2^N cycles of the previous one. If the PulseMultiplier block receives a second 1 on its input while it is producing an existing stream, its behavior is undefined.

The PulseMultiplier is a special version of the StretchPulse block.

Table 128.  Parameters for the PulseMultiplier Block
Parameter Description
N Specifies the output length pulse size 2^N.
Table 129.  Port Interface for the PulseDivider Block
Signal Direction Type Description
g Input Boolean or uint(1). Start of 2^N data block.
v Output uint(1). Data valid.

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