DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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Document Table of Contents Setting up Board Support Packages for Other Device Families


  1. In the scripts/post_flow.tcl file remove the following line:
    source $::env(ALTERAOCLSDKROOT)/ip/board/bsp/adjust_plls.tcl
  2. Open board.qsys file in Platform Designer
    1. Remove the kernel_clk_generator instance.
    2. Add instance of Intel PLL with one output clock. Set the reference clock frequency.
    3. Export the refclk clock input interface with kernel_pll_refclk name
    4. Connect outclk0 to the initial source of kernel_clk_generator.kernel_clk output.
    5. Connect the global_rest_in.out_reset output to reset input of PLL instance.
    6. Set the generated clock frequency
      Note: The design must meet timing on this clock domain. Intel advises that you use a low target frequency.