DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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6.12.26. Vector Sort—Iterative

This design sorts the values on the input vector from largest to smallest. The design is a masked subsystem that allows for sorting with either a comparator and mux block, or a minimum and a maximum block. The first implementation is more efficient. Both use the reconfigurable subsystem to choose between implementations using the BlockChoice parameter.

Folded designs repeatedly use a single dual sort stage. The throughput of the design is limited in the number of channels, vector width, and data rate. The data passes through the dual sort stage (vector width)/2 times. The vector sort design example uses full throughput with (vector width)/2 dual sort stages in sequence.

Look under the mask to view the implementation of reconfigurable subsystem templates and the blocks that reorder and interleave vectors.

The model file is demo_foldedsort.mdl.