DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
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3.5.1.1. DSP Builder Advanced Blockset Automatic Testbench Files

Table 6.   Files for an Automatic Testbench
File Name Description
<name>.vhd The HDL that is generated as part of the design (regardless of automatic testbenches).
<name>_stm.vhd An HDL file that reads in data files of captured Simulink simulation inputs and outputs on <name>
<name>_atb.vhd A wrapper HDL file that performs the following actions:
  • Declares <name>_stm and <name> as components
  • Wires the input stimuli read by <name>_atb to the inputs of <name> and the output stimuli and the outputs of <name> to a validation process that checks the captured Simulink data
  • Channel matches the VHDL simulation of <name> for all cycles where valid is high
  • Checks that the valid signals match
<input>/<output>.stm The captured Simulink data that the ChannelIn, ChannelOut, GPIn, GPout and IP blocks write.

Each block writes a single stimulus file capturing all the signals through it writing them in columns as doubles with one row for each timestep.

The device-level testbenches use these same stimulus files, following connections from device-level ports to where the signals are captured. Device-level testbenches are therefore restricted to cases where the device-level ports are connected to stimulus capturing blocks.