220.127.116.11. DSP Builder Advanced Blockset Automatic Testbench Files
|<name>.vhd||The HDL that is generated as part of the design (regardless of automatic testbenches).|
|<name>_stm.vhd||An HDL file that reads in data files of captured Simulink simulation inputs and outputs on <name>|
|<name>_atb.vhd||A wrapper HDL file that performs the following actions:
|<input>/<output>.stm||The captured Simulink data that the ChannelIn, ChannelOut, GPIn, GPout and IP blocks write.|
Each block writes a single stimulus file capturing all the signals through it writing them in columns as doubles with one row for each timestep.
The device-level testbenches use these same stimulus files, following connections from device-level ports to where the signals are captured. Device-level testbenches are therefore restricted to cases where the device-level ports are connected to stimulus capturing blocks.