DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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8.6.3. Implicit Delays in DSP Builder Designs

The DSP Builder scheduler may add extra delays on paths between the ChannelIn and ChannelOut blocks. The extra latency is the same for all such paths and is displayed on the ChannelOut block.

If the valid input drives directly the valid output, the delay on the valid signal matches the latency displayed on the ChannelOut block. It doesn't, if the valid output is generated in any other way, for example by using a Sequence block.

For example, the 4K FFT design example uses a Sequence block to drive the valid signal explicitly.

Figure 75. Sequence Block in the 4K FFT Design Example

The latency that the ChannelOut block reports is therefore not 4096 + the automatic pipelining value, but just the pipelining value.