DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9. About Folding

Folding optimizes hardware usage for low throughput systems, which have many clock cycles between data samples. Low throughput systems often inefficiently use hardware resources. When you map designs that process data as it arrives every clock cycle to hardware, many hardware resources may be idle for the clock cycles between data.

Folding allows you to create your design and generate hardware that reuses resources to create an efficient implementation.

The folding factor is the number of times you reuse a single hardware resource, such as a multiplier, and it depends on the ratio of the data and clock rates:

Folding factor = clock rate/data rate

DSP Builder offers ALU folding for folding factors greater than 500. With ALU folding, DSP Builder arranges one of each resource in a central arithmetic logic unit (ALU) with a program to schedule the data through the shared operation.