DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
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15.1.2. HDL Import

You can import VHDL, Verilog HDL, and System Verilog into DSP Builder designs when you add a HDL Import block to your design. You can only configure HDL Import blocks after you configure the HDL Import Config block.
Figure 109. HDL Import Block Parameters
Table 269.  HDL Import Parameters
Parameter Description
Instance Select from any instance in your imported HDL. Each HDL Import block must represent a unique instance.
Port DSP Builder automatically populates this column.
I/O Type DSP Builder determines the IO type based on the name of the port. You can change any entry to Input, Output, Clock, or Reset. HDL Import only allows one clock and one reset.
Data Type Informs Simulink and DSP Builder how they should interpret the ModelSim data. Set the Data Type of inputs to Inherit; the Data Type of outputs defaults to Signed. For Boolean or std_logic data type, select Unsigned with 0 fractional bits.