DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

3.1.2.7. Synchronization and Scheduling of Data with the Channel Signal

DSP Builder specifies the channel data separation per wire. The channel signal counts from 0 to ChanCycleCount – 1 in synchronization with the data. Thus, for ChanCycleCount = 1, the channel signal is the same as the channel count, enumerated 0 to ChanCount – 1.

For more than a single data wire, it is not equal to the channel count on data wires, but specifies the synchronous channel data alignment across all the data wires. For example,

Figure 14. Four Channels on One Wire with no invalid cycles.

For a single wire, the channel signal is the same as a channel count. However, for ChanWireCount > 1, the channel signal specifies the channel data separation per wire, rather than the actual channel number: it counts from 0 to ChanCycleCount –1 rather than 0 to ChanCount –1.

Figure 15. Four Channels on Two Wires with no invalid cycles.

The channel signal remains a single wire, not a wire for each data wire. It counts over 0 to ChanCycleCount –1.

Figure 16. Four Channels on Four Wires