DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4.5. FIR Filter with Exposed Bus

This design example is a multichannel single-rate FIR filter with rewritable coefficients. The initial configuration is a high-pass filter, but halfway through the testbench simulation, DSP Builder reconfigures it as a low-pass filter. The testbench feeds in the sum of a fast and a slow sine wave into the filter. The fast one emerges from the originally configured FIR filter; the slow one is all that is left after DSP Builder reconfigures the filter.

The model file is demo_fir_exposed_bus.mdl.