DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022
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3.7.3.2. Adding a DSP Builder Design to a Platform Designer System

You can use the DSP Builder design with other Platform Designer components that have Avalon Streaming (Avalon-ST) interfaces. You should design the system in Platform Designer, where you can connect the Avalon-ST interfaces. Hardware Tcl (_hw.tcl) files describe the interfaces.

The output of a DSP Builder design is a source of Avalon-ST data for downstream components. It supplies data (and corresponding valid, channel, and start and end of packet information) and accepts a Boolean flag input from the downstream components, which indicates the downstream block is ready to accept data.

The input of the DSP Builder design is a sink of Avalon-ST data for upstream components. It accepts data (and corresponding valid, channel, and start and end of packet information) and provides a Boolean flag output to the upstream component, which indicates the DSP Builder component is ready to accept data.

Procedure

  1. Simulate your design with Hardware Generation turned on in Control block.
    DSP Builder generates a <model>_hw.tcl file for the subsystem containing the Device block. This file marks the boundary of the synthesizable part of your design and ignores the testbench blocks.
  2. Add the synthesizable model to Platform Designer by including <model>_hw.tcl at the IP search path.

    Platform Designer native streaming data interface is the Avalon Streaming (Avalon-ST) interface, which DSP Builder advanced blockset does not support. The DSP Builder advanced blockset native interface <valid, channel, data> ports are exported to the top-level as conduit signals.

  3. Add DSP Builder components to Platform Designer by adding a directory that contains generated hardware to the IP Search Path in the Platform Designer Options dialog box.
  4. Define Avalon-ST interfaces to build system components that Platform Designer can join together.
    Upstream and downstream components are part of the system outside of the DSP Builder design.
  5. Register all paths across the DSP builder design to avoid algebraic loops.
    A design may have multiple Avalon-ST input and output blocks.
  6. Generate the Platform Designer system.
    In the hw.tcl file, the name of the Avalon-ST masked subsystem block is the name of the interface.
  7. Add FIFO buffers on the output (and if required on the input) to build designs that supporting backpressure, and declare the collected signals as an Avalon-ST interface in the hw.tcl file generated for the device level.
    These blocks do not enforce Avalon-ST behavior. They encapsulate the common Avalon-ST signals into an interface.