DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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6.13.20. QRD Solver

The QRD Solver reference design is a complete linear equations system solution using QR decomposition. The input of the design is a system matrix A [n x m] and input vector [b].
Figure 73. QRD SolverThe design decomposes the system matrix A to Q and R matrices using the Gram-Schmidt method. The design calculates the solution of the system by completing backward substitution.

The reference design is fully parameterizable over system dimensions n and m and the processing vector size, which defines the parallelization ratio of the dot product engine. This design implements parallel dot product engine using single-precision Multiply and Add blocks that perform most of the floating-point calculations. The design routes different phases of the calculation through these blocks with a controlling processor that executes a fixed set of microinstructions and generates operation indexes. The design implements the controlling processor using for-loop macro blocks, which allow very efficient, flexible, and high-level implementation of iterative operations.

This design uses the Run All Testbenches block to access enhanced features of the automatically generated testbench. An application-specific m-function verifies the simulation output, to correctly handle the complex results and the numerical approximation because of the floating-point format. Intel optimized the design for Intel® Stratix® 10 FPGAs. The design implements hardened floating-point operators in the FPGA DSP blocks.

Table 24.  Performance

Intel tested the design with Intel® Quartus® Prime v18.1.1 build 259, targeting a 1SG280LN3F43E2VG device

Matrix Size Parallel Processing Vector Size fMAX (MHz) Resources Throughput Latency
ALM DSPs M20K Cycles Matrices/s Cycles ms
512x256 512 320 461K (49%) 4,370 (76%) 1,313 (11%) 71,232 4,492 137,545 0.43
64x64 64 418 60.5 (6%) 562 (10%) 160 (1%) 7,920 52,777 12,392 0.03

The model file is demo_qrd_s10.mdl.