14.6.12. Single-Cycle Latency Latch (latch_1L)
These latches work for any data type, and for vector and complex numbers.
Right-click on the block and select Look Under Mask, for the structure.
The e signal is a ufix(1) enable signal. When e is high, the latch_1 block delays data from input d by one cycle and feeds through to output q. When e is low, the latch_1 block holds the last output.
A switch in e means the latch_1 block holds the output one cycle later.