DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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14.4.50. Sample Delay (SampleDelay)

The SampleDelay block outputs a delayed version of the input.
Note: SampleDelay blocks might not reset to zero. Do not use designs that rely on SampleDelays output of zero after reset. Use the valid signal to indicate valid data and its propagation through the design.
Table 231.  Parameters for the SampleDelay Block
Parameter Description
Output data type mode Determines how the block sets its output data type:
  • Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types.
  • Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected.This option reinterprets the output bit pattern from the LSB up according to the specified type.
  • Boolean: the output type is Boolean.
  • Single: single floating-point data.
  • Double: double floating-point data.
Output data type Specifies the output data type. For example, sfix(16), uint(8).
Output scaling value Specifies the output scaling value. For example, 2^-15.
Number of delays Specifies the number of samples to delay.
Minimum delay Checks if the delay can grow as needed, so that the specified length becomes the lower bound.
Equivalence group Sample delays that share the same equivalence group string grow by the same increment.
Table 232.  Port Interface for the SampleDelay Block
Signal Direction Type Description Vector Data Support Complex Data Support
a Input Any fixed- or floating-point type Data input Yes Yes
q Output Derived fixed- or floating-point type Data output Yes Yes