DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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6.11.3. 2-Antenna DUC for WiMAX

This design example shows how to build a 2-antenna DUC to meet a WiMAX specification.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus a ChanView block that deserializes the output bus.

The DUCChip subsystem includes a Device block and a lower level DUC2Antenna subsystem.

The DUC2Antenna subsystem includes InterpolatingFIR, SingleRateFIR, Const, ComplexMixer, NCO, and Scale blocks.

The model file is demo_wimax_duc.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.