DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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9.1.1. ALU Folding Limitations

Avoid using ALU folding with designs that use many data types. ALU folding is ideal for large designs with a uniform data type, such as single-precision floating-point. The design uses less logic when creating a single hardware resource for an operation in the ALU that it can share across the design.

For designs that use more than one data type, a Convert block between two data types uses more resources if the design requires saturation and rounding. An unbiased rounding operation uses more resources than a biased rounding mode.

Some DSP Builder blocks store state, for example:

  • Sample Delay
  • Counter
  • DualMem
  • FIFO

With ALU folding, any blocks that store state have a separate state for each channel. DSP Builder only updates the state for a channel when the system processes the channel. Thus, a sample delay delays a signal until processing the next data sample. For 200 clock cycles to a data period, DSP Builder delays the signal for the 200 clock cycles. Also, data associated with one channel cannot affect the state associated with any other channel. Changing the number of channels does not affect the behavior of the design.

Note: For designs without ALU folding, state is associated with a block, which you can update in any clock cycle. Data input with channel 0 can affect state that then affects a computation with data input with channel 1.