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- 14.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)
- 14.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle)
1. About DSP Builder for Intel® FPGAs
|Intel® Quartus® Prime Design Suite 21.3|
You can create designs without needing detailed device knowledge and generate designs that run on a variety of FPGA families with different hardware architectures. DSP Builder allows you to manually describe algorithmic functions and apply rule-based methods to generate hardware optimized code. The advanced blockset is particularly suited for streaming algorithms characterized by continuous data streams and occasional control. For example, use DSP Builder to create RF card designs that comprise long filter chains.
After specifying the desired clock frequency, target device family, number of channels, and other top-level design constraints, DSP Builder pipelines the generated RTL to achieve timing closure. By analyzing the system-level constraints, DSP Builder can optimize folding to balance latency versus resources, with no need for manual RTL editing.
DSP Builder advanced blockset includes its own timing-driven IP blocks that can generate high performance FIR, CIC, and NCO models.
- DSP Builder for Intel FPGAs Features
- DSP Builder for Intel FPGAs Design Structure
Organize your DSP Builder designs into hierarchical Simulink subsystems. Every top-level design must contain a Control block; the synthesizable top-level design must contain a Device block.
- DSP Builder for Intel FPGAs Libraries
- DSP Builder for Intel FPGAs Device Support
DSP Builder supports devices in Intel® Quartus® Prime Pro Edition.
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