DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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Document Table of Contents

1. About DSP Builder for Intel® FPGAs

Updated for:
Intel® Quartus® Prime Design Suite 21.3
DSP Builder is a high-level synthesis technology that optimizes the high-level, untimed netlist into low level, pipelined hardware for your target FPGA device and desired clock rate. DSP Builder for Intel® FPGAs consists of several Simulink* libraries that allow you to implement DSP designs quickly and easily. DSP Builder implements the hardware as VHDL or Verilog HDL with scripts that integrate with the Intel® Quartus® Prime software and the ModelSim* simulator.

You can create designs without needing detailed device knowledge and generate designs that run on a variety of FPGA families with different hardware architectures. DSP Builder allows you to manually describe algorithmic functions and apply rule-based methods to generate hardware optimized code. The advanced blockset is particularly suited for streaming algorithms characterized by continuous data streams and occasional control. For example, use DSP Builder to create RF card designs that comprise long filter chains.

After specifying the desired clock frequency, target device family, number of channels, and other top-level design constraints, DSP Builder pipelines the generated RTL to achieve timing closure. By analyzing the system-level constraints, DSP Builder can optimize folding to balance latency versus resources, with no need for manual RTL editing.

DSP Builder advanced blockset includes its own timing-driven IP blocks that can generate high performance FIR, CIC, and NCO models.