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- 14.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)
- 14.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle)
6.13.12. 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 307.2 MHz with Total Rate Change 40
The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. A Spectrum Scope block computes and displays the periodogram of the outputs from the two antennas.
The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC subsystem that contains InterpolatingFIR, InterpolatingCIC, NCO, ComplexMixer, and Scale blocks.
The FIR and CIC filters implement an interpolating filter chain that up converts the 16-channel input data from a frequency of 3.84 MSPS to a frequency of 153.6 MSPS (a total interpolation factor of 40).
The complex mixer and NCO modulate the four channel baseband input signal onto the IF region. The design configures the NCO with four channels to provide four pairs of sine and cosine waves at frequencies of 12.5 MHz, 17.5 MHz, 22.5 MHz, and 27.5 MHz, respectively. The NCO has the same sample rate (153.6 MSPS) as the final interpolated output sample rate from the last CIC filter in the interpolating filter chain.
The Sync subsystem shows how to manage two data streams that come together and Synchronize. The design writes data from the NCOs to a memory with the channel as an address. The data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly.
The CarrierSum and SignalSelector subsystems sum up the right modulated signals to the designated antenna.
A system clock rate of 307.2 MHz, which is 80 times the input sample rate, drives the design on the FPGA, which the Device block defines inside the DUC subsystem. The higher clock rate can potentially allow resource re-use in other modules of a digital system implemented on an FPGA.
The model file is mcducmix80x40R.mdl.
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