DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 3/23/2022

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Document Table of Contents System-In-The-Loop Parameters

The design interface settings only generate appropriate adapters between the DSP Builder ChannelIn and ChannelOut interfaces and test Avalon-ST interface. The hardware platform always runs at fixed clock rate.
Table 12.  System-In-The-Loop Parameters
Section Option Description
BSP Settings BSP Select the target BSP you want to run the hardware test on.
Device Device on the selected board.
BSP Memory


Total Memory Size Specify the total size for test memory to use.
Input Memory Size Specify the amount of memory (from total memory size) for storing input test data. The remaining memory is for storing output data.

You might require several iterations to load and process all input test vectors because of memory limitations.

Design Interface Clock Rate Specify the same value as in the DSP Builder block setup file.
Sample Rate Specify the same value as in the DSP Builder block setup file.
Number of Channels The number of channels for the DSP Builder block. Specify the same value as in the DSP Builder block setup file.
Frame Size This value represents a number of valid data samples that you should supply to the DSP Builder block without timing gaps in between.

If this value is more than 1, the wizard inserts a specific block in between test data provider and the DSP Builder block. This block enables data transmission to the DSP Builder block only when the specified amount of data is already available.

An example of such a design is a folded multichannel design.

- Destination


Specify the directory where DSP Builder should generate the system- in-the-loop related files.

You should change to this directory to simulate the system-in-the-loop generated model with an FPGA proxy.

Table 13.  System-In-The-Loop Run Settings
Setting Description
Select SIL Flow Select the system- in-the-loop flow to use. The options are:

Run Test Vectors runs all test vectors through the hardware verification system. The test vectors are based on simulation data recorded in DSP Builder .stm format files during Simulink simulation.

Step Through Simulation allows processing every different set of valid input data on hardware separately, while simulating a design from Simulink. The wizard generates a separate model <model_name> _SIL in the SIL destination directory, which you should use for hardware verification. The original DSP Builder device level block is replaced with a specific block providing communication with the FPGA.

You should change to SIL destination directory before you can simulate this model.

If you change the flow, regenerate and recompile the system into a new destination directory.

Generate Generates the infrastructure, files, and blocks for the hardware verification platform.
Compile Compiles the entire hardware verification system in the Quartus Prime software to the generation configuration file.

Allow at least 10-15 minutes for this step to run (more time for large DSP Builder designs). During this time the MATLAB input interface is unavailable.

Select JTAG Cable Press Scan to scan available JTAG connections for programming the board.

Choose the required JTAG cable from the discovered list.

Program Program the board through selected JTAG cable.

Go directly to this step if you have a pregenerated design with no changes with the flow parameters and in DSP Builder design under test.

Run Run the test on hardware. Run Test Vectors only.

The hardware test automatically detects and executes write requests over the DSP Builder autogenerated Avalon memory-mapped agent interface. The wizard cannot keep the sequence of transfers for write requests over Avalon memory-mapped agent interface and the DSP Builder data interface on hardware exactly the same as during simulation. Therefore, you may see data mismatches for a few sets of output samples at points where write requests are issued.

Compare Compare the hardware verification results with simulation outputs. Run Test Vectors only.

The wizard compares only valid output samples.

Simulate <original_model>_SIL system During simulation, the FPGA proxy block that replaces the original DSP Builder design in the system-in-the-loop:
  • Every time you update inputs, it loads data to DSP Builder if valid input is high
  • Every time you request outputs, it populates outputs with data read from hardware if output memory contains valid sample.

    Step through simulation only.

    Because the FPGA proxy updates its output only with valid samples, you see the same results repeated on the outputs until hardware has a new valid set of data. This behavior may differ from simulation results, where outputs are populated at every simulation cycles with available values.