DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook
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6.4.15. Root-Raised Cosine FIR Filter
The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_fir_rrc.m script.
The FilterSystem subsystem includes the Device and Decimating FIR blocks.
The model file is demo_fir_rrc.mdl.