Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

8.3.2.2. L3 Address Space

The L3 address space is 4 GB and applies to all L3 masters except the MPU subsystem.

The L3 address space configurations contain the regions shown in the following table:

Table 34.  L3 Address Space Regions
Description Condition Base Address End Address Size
SDRAM window (without on-chip RAM) When remap.nonmpuzero 14 is clear 0x00000000 0xBFFFFFFF 3 GB
On-chip RAM When remap.nonmpuzero 14 is set 0x00000000 0x0000FFFF 64 KB
SDRAM window (with on-chip RAM) When remap.nonmpuzero 14 is set 0x00010000 0xBFFFFFFF 3145664 KB

= 3 GB - 64 KB

ACP window Always visible 0x80000000 0xBFFFFFFF 1 GB
HPS-to-FPGA When remap.hps2fpga 14 is set. Not visible to FPGA-to-HPS bridge. 0xC0000000 0xFBFFFFFF 960 MB
System trace macrocell Always visible to DMA and FPGA-to-HPS 0xFC000000 0xFEFFFFFF 48 KB
Debug access port Not visible to master peripherals. Always visible to other masters. 0xFF000000 0xFF1FFFFF 2 MB
Lightweight HPS-to-FPGA Not visible to master peripherals. Visible to other masters when remap.hps2fpga 14 is set. 0xFF200000 0xFF3FFFFF 2 MB
Peripherals Not visible to master peripherals. Always visible to other masters. 0xFF400000 0xFFFCFFFF 12096 KB
On-chip RAM Always visible 0xFFFF0000 0xFFFFFFFF 64 KB
The boot ROM and internal MPU registers (SCU and L2) are not accessible to L3 masters.

SDRAM Window Region

The SDRAM window region is 3 GB and provides access to the bottom 3 GB of the SDRAM address space. Any L3 master can access a cache-coherent view of SDRAM by performing a cacheable access through the ACP.

On-Chip RAM Region

The system interconnect remap register, in the l3regs group, determines if the 64 KB starting at address 0x0 is mapped to the on-chip RAM or the SDRAM. The SDRAM is mapped to address 0x0 on reset.

ACP Window Region

The ACP window region is 1 GB and provides access to a configurable gigabyte-aligned region of the MPU address space. Registers in the ACP ID mapper control which gigabyte-aligned region of the MPU address space is accessed by the ACP window region. The ACP window region is used by L3 masters to perform coherent accesses into the MPU address space. For more information about the ACP ID mapper, refer to the Cortex-A9 Microprocessor Unit Subsystem chapter.

HPS-to-FPGA Slaves Region

The HPS-to-FPGA slaves region provides access to 960 MB of slaves in the FPGA fabric through the HPS-to-FPGA bridge.

Lightweight HPS-to-FPGA Slaves Region

The lightweight HPS-to-FPGA slaves provide access to slaves in the FPGA fabric through the lightweight HPS-to-FPGA bridge.

Peripherals Region

The peripherals region includes slaves connected to the L3 interconnect and L4 buses.

On-Chip RAM Region

The on-chip RAM is always mapped (independent of the boot region contents).
14 For details about the remap register, refer to "Bit Fields for Modifying the Memory Map"