Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

9.3.5.2. HPS-to-FPGA Bridge Clocks and Resets

The master interface into the FPGA fabric operates in the h2f_axi_clk clock domain. The h2f_axi_clk clock is provided by user logic. The slave interface of the bridge in the HPS logic operates in the l3_main_clk clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any clock domain, asynchronous from the HPS.

The HPS-to-FPGA bridge has one reset signal, hps2fpga_bridge_rst_n. The reset manager drives this signal to the HPS-to-FPGA bridge on a cold or warm reset.