Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683063
Date 1/11/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices 3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices 4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices 5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices 6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices 8. Interface Signals Description 9. Configuration Registers Description 10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives 11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Testing the Design in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.4. Simulation x
2.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 2.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
2.5. Hardware Testing x
2.5.1. Test Cases 2.5.2. Signal Tap Debug Signals
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Cases 3.5.2. Signal Tap Debug Signals
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking and Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Cases 4.5.2. Signal Tap Debug Signals
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signal 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme 5.3.4. Partial Reconfiguration Ready
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 5.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme 6.3.4. Partial Reconfiguration Ready 6.3.5. Timing Constraints
6.5. Hardware Testing x
6.5.1. Test Procedure
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.4. Simulation x
7.4.1. Test Case
7.5. Hardware Testing x
7.5.1. Test Procedure
8. Interface Signals Description x
8.1. Clock and Reset Interface Signals 8.2. Avalon® Memory-Mapped Interface Signals 8.3. Avalon® Streaming Interface Signals 8.4. PHY Interface Signals 8.5. Status Interface 8.6. IEEE 1588v2 Timestamp Interface Signals 8.7. Packet Classifier Interface Signals 8.8. ToD Interface Signals
9. Configuration Registers Description x
9.1. Register Access Definition 9.2. Low Latency Ethernet 10G MAC 9.3. PHY 9.4. Transceiver Reconfiguration 9.5. TOD
9.3. PHY x
9.3.1. 1G/10G PHY 9.3.2. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

1.4.1. Procedure

You can compile and test the design in the supported Intel FPGA development kit.
  1. Launch the Intel® Quartus® Prime software and open the design example project file. Select Processing > Start Compilation to compile the design example.
    The timing constraints for the design example and the design components are automatically loaded during compilation.
  2. Connect the development board to the host computer.
  3. Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example.
    Note: For the frequencies to set, refer to the Hardware Testing section in the respective design example chapter.
  4. In the Intel® Quartus® Prime software, select Tools > Programmer to configure the FPGA on the development board using the generated .sof file.
  5. Reset the system by pressing the PB0 push button.
  6. In the Intel® Quartus® Prime software, select Tools > System Debugging Tools > System Console to launch the system console.
  7. Change the working directory to <Example Design>\hwtesting\system_console .
  8. Initialize the design command list by running this command: source main.tcl.
    Note: For a design example that does not provide the main.tcl file, refer to the Hardware Testing section in the respective design example chapter.
You can now run any of the predefined hardware tests from the System Console.
Observe the test results displayed.
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