Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

7.3.1. Design Components

Table 27.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • Use legacy XGMII Interface: Not selected
  • Use legacy Avalon Memory-Mapped Interface: Not selected
  • Use legacy Avalon Streaming Interface: Selected
PHY The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
  • Speed: 10M/100M/1G/2.5G/5G/10G
  • Connect to MGBASE-T PHY: Not selected
  • Connect to NBASE-T PHY: Selected
  • Reference clock frequency for 10GbE (MHz): 644.53125
  • Enable Native PHY Debug Master Endpoint: Not selected
  • Enable capability registers: Not selected
  • Enable control and status registers: Not selected
  • Enable PRBS soft accumulators: Not selected
Channel address decoder Decodes the addresses of the components in each Ethernet channel, such as PHY and LL 10GbE MAC.
Multi-channel address decoder Decodes the addresses of the components used by all channels , such as the Master ToD module.
Top address decoder Decodes the addresses of the top-level components, such as the Traffic Controller.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® FPGA IP . Resets the transceiver.
ATX PLL Generates a TX serial clock for the Intel® Arria® 10 10G transceiver.
Core fPLL Generates clocks for all design components.

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