1.2.2. Design Example Parameters
|Select Design||Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design.|
|Example Design Files||
The files to generate for the different development phase.
|Generate File Format||The format of the RTL files for simulation—Verilog or VHDL.|
|Select Board||Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.
If this menu is not available, there is no supported board for the options that you select.
Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit : This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel® FPGA IP development kit. If your board revision has a different device grade, you can change the target device.
Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel® FPGA IP device, a custom designed board with Intel® FPGA IP device, or a standard Intel® FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit.
No Development Kit : This option excludes the hardware aspects for the design example.
|Change Target Device||Select this parameter to display and select all devices for the Intel® FPGA IP development kit.|
|Specify Number of Channels||The number of Ethernet channels.|
|Enable Native PHY Debug Master Endpoint (NPDME)||Turn on this option to enable the Transceiver Native PHY Debug Master Endpoint (NPDME) feature.
Note: This option is only available from Intel® Quartus® Prime Pro Edition version 17.0 onwards
|Partial Reconfiguration Ready||When this option is enabled, the generated hierarchy of the design example is compliance with the partial reconfiguration flow, where there is clear separation between hard IP and soft IP, without any functionality changes. Hard IPs such as Native PHY, JTAG, transmitter PLL, and FPLL are instantiated at the top-level wrapper of design example.
Note: This option is only available from Intel® Quartus® Prime Pro Edition version 17.1 onwards
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