Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

6.3.1. Design Components

Table 24.  Design Components
Component Description

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 1G/2.5G/10G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • All Legacy Ethernet 10G MAC Interfaces options: Selected
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver.
Avalon® Memory-Mapped Mux Transceiver Reconfig Provides the transceiver reconfig block and system console access to the PHY's Avalon® memory-mapped interface.
Transceiver Reconfig Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.
ATX PLL Generates a TX serial clock for the Intel® Arria® 10 2.5G and 10G transceiver.
fPLL Generates a TX serial clock for the Intel® Arria® 10 1G transceiver.

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