Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

7.7. Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.

Table 29.  Register Map
Byte Offset Block
0x00_0000 Reserved
Channel 0
0x02_0000 Reserved
0x02_4000 PHY
0x02_6000 Native PHY Reconfiguration
0x02_8000 MAC
Channel 1
0x03_0000 Reserved
0x03_4000 PHY
0x03_6000 Native PHY Reconfiguration
0x03_8000 MAC
Traffic Controller
0x10_0000 Traffic Controller