Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

3.4. Simulation

The simulation test cases demonstrate how the channel speed and the configuration of the PHY are changed. These test cases use circular loopback on the total number of Ethernet channels. The following table describes the steps to change the speed and configuration.
Table 11.  Ethernet Operations
Operation Description
Configuring the PHY speed. Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), or 1G1000Base-X.
Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. Write one of the following values to the PHY's register at address offset 0x12C0.
  • 0x01: Turn on the auto-detection mode. In this mode, the PHY automatically detects the speed.
  • 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps.
  • 0x41: Turn off the auto-detection mode and set the speed to 10 Gbps.


To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11

To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01