Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

3.7. Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.

Table 16.   Register Map
Byte Offset Block
0x00_0000 Client logic
0x00_F000 Reserved
0x01_0000 Master TOD
Channel 0
0x02_0000 Reserved
0x02_4000 PHY
0x02_7800 10G TOD
0x02_7900 1G TOD
0x02_8000 LL 10GbE MAC
Channel 1
0x03_0000 Reserved
0x03_4000 PHY
0x03_7800 10G TOD
0x03_7900 1G TOD
0x03_8000 LL 10GbE MAC
.. and so forth up to Channel 11.
0x0E_0000 onwards Client Logic